yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added support for "file names with blanks"	Clifford Wolf	2015-04-08
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*	Removed "techmap -share_map" (use "-map +/filename" instead)	Clifford Wolf	2015-04-08
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*	Added %M and %C select operators	Clifford Wolf	2015-04-07
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*	Added "pmuxtree" command	Clifford Wolf	2015-04-07
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*	Added "chparam -list"	Clifford Wolf	2015-04-07
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*	Added decoder generation to "muxcover"	Clifford Wolf	2015-04-07
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*	Added hashlib support for std::tuple<>	Clifford Wolf	2015-04-07
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*	Added "muxcover" command	Clifford Wolf	2015-04-07
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*	Added pool<K>::pop()	Clifford Wolf	2015-04-07
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*	typo fix	Clifford Wolf	2015-04-07
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*	Added "chparam" command	Clifford Wolf	2015-04-07
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*	Added support for initialized xilinx brams	Clifford Wolf	2015-04-06
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*	Added support for initialized brams	Clifford Wolf	2015-04-06
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*	Added Xilinx test case for initialized brams	Clifford Wolf	2015-04-06
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*	Added Xilinx bram black-box modules	Clifford Wolf	2015-04-06
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*	Added "port_directions" to write_json output	Clifford Wolf	2015-04-06
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*	Avoid parameter values with size 0 ($mem cells)	Clifford Wolf	2015-04-05
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*	make all vector-size related integer params in $mem sim model signed	Clifford Wolf	2015-04-05
\| \| \| \| \| \|	this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.
*	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	Clifford Wolf	2015-04-05
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*	Added "dffinit", Support for initialized Xilinx DFF	Clifford Wolf	2015-04-04
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*	Added "init" attribute support to verilog backend	Clifford Wolf	2015-04-04
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*	appnote 012 fix	Clifford Wolf	2015-04-04
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*	Appnote 012	Clifford Wolf	2015-04-04
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*	Updated ABC to 51705b168d7a	Clifford Wolf	2015-04-04
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*	Merge pull request #55 from ahmedirfan1983/master	Clifford Wolf	2015-04-04
\|\ \| \| \| \|	added appnote and impr in btor
\| *	Update README	Ahmed Irfan	2015-04-03
\| \| \| \| \| \|	corrected url
\| *	Delete btor.ys	Ahmed Irfan	2015-04-03
\| \| \| \| \| \|	.ys script not needed
\| *	Update README	Ahmed Irfan	2015-04-03
\| \| \| \| \| \|	pmux cell is implemented
\| *	separated memory next from write cell	Ahmed Irfan	2015-04-03
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\| *	Merge branch 'master' of https://github.com/cliffordwolf/yosys	Ahmed Irfan	2015-04-03
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* \|	documentation improvements	Clifford Wolf	2015-03-29
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* \|	Ignore celldefine directive in verilog front-end	Clifford Wolf	2015-03-25
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* \|	Fixes in cmos_cells.v	Clifford Wolf	2015-03-25
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* \|	Fixed detection of absolute paths in ABC for win32	Clifford Wolf	2015-03-22
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* \|	Added blif reference to appnote 010	Clifford Wolf	2015-03-22
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* \|	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2015-03-20
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\| * \|	Fixed handling of quotes in liberty parser	Clifford Wolf	2015-03-18
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* \| \|	fix for python 2.6.6	Clifford Wolf	2015-03-20
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* \|	Added hierarchy -auto-top	Clifford Wolf	2015-03-18
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* \|	Added Verilog backend $dffsr support	Clifford Wolf	2015-03-18
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* \|	Documentation for JSON format, added attributes	Clifford Wolf	2015-03-06
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* \|	Added very first version of "synth_ice40"	Clifford Wolf	2015-03-05
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* \|	Fixed bug in "hierarchy" for parametric designs	Clifford Wolf	2015-03-04
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* \|	Json bugfix	Clifford Wolf	2015-03-03
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* \|	Json backend improvements	Clifford Wolf	2015-03-03
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* \|	Added write_blif -attr	Clifford Wolf	2015-03-02
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* \|	Added JSON backend	Clifford Wolf	2015-03-02
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* \|	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	Clifford Wolf	2015-03-01
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* \|	Added $assume support to write_smt2	Clifford Wolf	2015-02-26
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* \|	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26
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