Commit message (Expand)AuthorAge
* Added tests/vloghtb/test_share.shClifford Wolf2014-07-20
* Added tests/share for testing "share" supercell creationClifford Wolf2014-07-20
* Added "share" supercell creationClifford Wolf2014-07-20
* Added removing of always inactive cells to "share" passClifford Wolf2014-07-20
* Progress in "share" passClifford Wolf2014-07-20
* Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversionClifford Wolf2014-07-20
* Added SIZE() macroClifford Wolf2014-07-20
* Added log_cell()Clifford Wolf2014-07-20
* Progress in "share" passClifford Wolf2014-07-20
* Added tests/vloghtbClifford Wolf2014-07-20
* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...Clifford Wolf2014-07-20
* Added support for $bu0 to verilog backendClifford Wolf2014-07-20
* Started to implement real resource sharingClifford Wolf2014-07-19
* Fixed log_id() memory corruptionClifford Wolf2014-07-19
* Improved memory_share log messagesClifford Wolf2014-07-19
* More verbose memory_share help messageClifford Wolf2014-07-19
* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-19
* Added ModWalker helper classClifford Wolf2014-07-19
* Some "const" cleanups in SigMapClifford Wolf2014-07-19
* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-19
* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-18
* Improved seeding of color rng in show commandClifford Wolf2014-07-18
* Only create collision detect logic in memory_share if necessaryClifford Wolf2014-07-18
* Bugfix in tests/memories/run-test.shClifford Wolf2014-07-18
* added tests/memoriesClifford Wolf2014-07-18
* Added memory_shareClifford Wolf2014-07-18
* Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>Clifford Wolf2014-07-18
* Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN portClifford Wolf2014-07-18
* Added function-like cell creation helpersClifford Wolf2014-07-18
* Added log_id() helper functionClifford Wolf2014-07-18
* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-17
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
* Fixed simlib.v model for $memClifford Wolf2014-07-17
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
* Improved opt_reduce handling of mem wr_en mux bitsClifford Wolf2014-07-17
* Fixed RTLIL::SigSpec::append_bit() for appending constantsClifford Wolf2014-07-17
* Added support for "blackbox" attribute to iopadmapClifford Wolf2014-07-17
* Added support for "blackbox" attribute to flatten/techmapClifford Wolf2014-07-17
* Added "inout" ports support to read_libertyClifford Wolf2014-07-16
* Set blackbox attribute in "read_liberty -lib"Clifford Wolf2014-07-16
* Fixed spelling of "direction" in read_liberty messagesClifford Wolf2014-07-16
* Merged new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
| * Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
| * improved opt_reduce for $mem/$memwr WR_EN multiplexersClifford Wolf2014-07-16
| * changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
| * Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-16
| * Updated simlib to new $mem/$memwr interfaceClifford Wolf2014-07-16
| * Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-16
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-16