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Debian dgit repo for package yosys
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Added "test_cell -const"
Clifford Wolf
2014-09-08
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Using maccmap for $macc and $mul techmap
Clifford Wolf
2014-09-07
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Added 'techmap_maccmap' techmap attribute
Clifford Wolf
2014-09-07
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Added "maccmap" command
Clifford Wolf
2014-09-07
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Added "test_cell -nosat"
Clifford Wolf
2014-09-07
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Various bug fixes (related to $macc model testing)
Clifford Wolf
2014-09-06
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Added $macc eval model
Clifford Wolf
2014-09-06
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Added $macc SAT model
Clifford Wolf
2014-09-06
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Fixed $clog2 (off by one error)
Clifford Wolf
2014-09-06
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Added $macc simlib model (also use as techmap rule for now)
Clifford Wolf
2014-09-06
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Fixed assignment of out-of bounds array element
Clifford Wolf
2014-09-06
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Added $macc cell type
Clifford Wolf
2014-09-06
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Fixed autotest for non-basename arguments
Clifford Wolf
2014-09-06
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2014-09-06
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Merge pull request #38 from rubund/master
Clifford Wolf
2014-09-06
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Corrected spelling mistakes found by lintian
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Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
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/
/
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*
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Added tests/various/constmsk_test.ys
Clifford Wolf
2014-09-04
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Added "test_cell -script"
Clifford Wolf
2014-09-06
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*
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Fixed "opt_const -fine" for $pos cells
Clifford Wolf
2014-09-04
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Removed $bu0 cell type
Clifford Wolf
2014-09-04
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Using $pos models for $bu0
Clifford Wolf
2014-09-03
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Fixed "test_cells -vlog"
Clifford Wolf
2014-09-03
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Fixes in $alu SAT- and eval-models
Clifford Wolf
2014-09-03
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Undef-related fixes in simlib $alu model
Clifford Wolf
2014-09-02
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Improvements in "test_cell -vlog"
Clifford Wolf
2014-09-02
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Added test_cell -vlog
Clifford Wolf
2014-09-02
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Create a default selection stack in RTLIL::Design::Design()
Clifford Wolf
2014-09-02
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Small bug fixes in $not, $neg, and $shiftx models
Clifford Wolf
2014-09-02
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Added SAT testing to test_cell eval stage
Clifford Wolf
2014-09-02
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Removed references to yosys-svgviewer from docs
Clifford Wolf
2014-09-02
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Removed yosys-svgviewer
Clifford Wolf
2014-09-02
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Using "xdot" instead of "yosys-svgviewer" in show command
Clifford Wolf
2014-09-02
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Added $alu support to test_cell
Clifford Wolf
2014-09-01
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Added ConstEval model for $alu cells
Clifford Wolf
2014-09-01
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*
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Added SAT model for $alu cells
Clifford Wolf
2014-09-01
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*
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Fixed "test_cell -simlib all"
Clifford Wolf
2014-09-01
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Added "test_cell -simlib -v"
Clifford Wolf
2014-09-01
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Added "techmap -autoproc"
Clifford Wolf
2014-09-01
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Fixes in old SAT example.ys
Clifford Wolf
2014-09-01
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Moved "share" and "wreduce" to passes/opt/
Clifford Wolf
2014-09-01
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Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵
Clifford Wolf
2014-09-01
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RTLIL::SigChunk::data
*
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Added eval testing to test_cell
Clifford Wolf
2014-08-31
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*
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Fixed return size of const_*() eval functions
Clifford Wolf
2014-08-31
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*
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Added RTLIL::Const::size()
Clifford Wolf
2014-08-31
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Added eval model for $lut cells
Clifford Wolf
2014-08-31
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Typo fixes in cell->*Param() API
Clifford Wolf
2014-08-31
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Added $lut support in test_cell, techmap, satgen
Clifford Wolf
2014-08-31
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Added design->scratchpad
Clifford Wolf
2014-08-30
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Added $alu cell type
Clifford Wolf
2014-08-30
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Added autotest -e (do not use -noexpr on write_verilog)
Clifford Wolf
2014-08-30
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