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* Progress on AppNote 011Clifford Wolf2013-11-29
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* Using RTLIL::id2cstr for prompt printingClifford Wolf2013-11-29
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* Added dump -m and -n optionsClifford Wolf2013-11-29
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* Progress on AppNote 011Clifford Wolf2013-11-28
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* Merge pull request #17 from mschmoelzer/masterClifford Wolf2013-11-28
|\ | | | | Include unistd.h in svgview.cpp (required for getcwd() function)
| * Include unistd.h in svgview.cpp (required for getcwd() function)Martin Schmölzer2013-11-28
| | | | | | | | | | | | This fixes compilation on Arch Linux, which otherwise fails. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
* | Fixed temp net name generation in rtlil process generator for abbreviated ↵Clifford Wolf2013-11-28
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* | Added pattern support to "ls" commandClifford Wolf2013-11-28
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* | Improved ID matching scheme in select (and thus for all commands)Clifford Wolf2013-11-28
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* | Fixes and improvements in "show" commandClifford Wolf2013-11-28
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* | More progress on AppNote 011Clifford Wolf2013-11-28
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* | Added "src" attribute to processesClifford Wolf2013-11-28
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* | Started writing appnote 011Clifford Wolf2013-11-28
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* | Added support for "show -pause" and "show -format dot"Clifford Wolf2013-11-28
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* Added QGraphicsWebView to yosys-svgviewerClifford Wolf2013-11-28
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* Updated ABC to 9241719523f6Clifford Wolf2013-11-28
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* Added some svgviewer code for possible future switch to QGraphicsWebViewClifford Wolf2013-11-27
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-11-27
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| * Set version number to 0.1.0+Clifford Wolf2013-11-27
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* | Tighter integration of ABC buildClifford Wolf2013-11-27
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* Started implementing undef support in "sat" commandClifford Wolf2013-11-25
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* Bugfixes in new "stat" commandClifford Wolf2013-11-25
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* Added "stat" commandClifford Wolf2013-11-25
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* Improvements in satgen undef handlingClifford Wolf2013-11-25
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* Improvements in satgen undef handlingClifford Wolf2013-11-25
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* Added ezsat vec_const() apiClifford Wolf2013-11-25
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* Started implementing undef handling in satgenClifford Wolf2013-11-25
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* Removed undef feature from ezsat apiClifford Wolf2013-11-25
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* Using simplemap mappers from techmapClifford Wolf2013-11-24
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* Added simplemap passClifford Wolf2013-11-24
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* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
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* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
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* Added techmap -D and -I optionsClifford Wolf2013-11-24
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* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
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* Added "techmap -share_map" optionClifford Wolf2013-11-24
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* Early wire/reg/parameter width calculation in ast/simplifyClifford Wolf2013-11-24
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* Updated TODOsClifford Wolf2013-11-24
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* Fixed xilinx/example_sim_counter test benchClifford Wolf2013-11-24
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* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-24
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* Added support for signed parameters in ilangClifford Wolf2013-11-24
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* Removed now obsolete test casesClifford Wolf2013-11-24
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
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* Added modelsim support to autotestClifford Wolf2013-11-24
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* Fixed "flatten" top-module detection: Only use on fully selected designsClifford Wolf2013-11-24
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* Fixed "make install" dependenciesClifford Wolf2013-11-24
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* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-24
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* Updated command-reference-manual.texClifford Wolf2013-11-23
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* AppNote 010 typo fixes and correctionsClifford Wolf2013-11-23
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* AppNote 010 progressClifford Wolf2013-11-23
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