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* Another fix in mem2reg ast simplify logicClifford Wolf2013-03-24
* Added -colors option to show commandClifford Wolf2013-03-24
* Added hansimem testcase (memory with async reset)Clifford Wolf2013-03-24
* Improved mem2reg handling in ast simplifierClifford Wolf2013-03-24
* Fixed gcc build (intersynth backend)Clifford Wolf2013-03-23
* Tiny fixes to verilog parserClifford Wolf2013-03-23
* Various improvements in intersynth backendClifford Wolf2013-03-23
* Added intersynth backendClifford Wolf2013-03-23
* Added help -write-tex-command-reference-manual optionClifford Wolf2013-03-21
* Added eclipse CDT project files to .gitignoreClifford Wolf2013-03-21
* Added -S option for simple synthesis to gate logicClifford Wolf2013-03-21
* Avoid verilog-2k in verilog backendClifford Wolf2013-03-21
* Disabled the per-default dumping of ILANG codeClifford Wolf2013-03-21
* Added -nomap option to memory passClifford Wolf2013-03-21
* Merge branch 'hansiglaser-master'Clifford Wolf2013-03-19
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| * added optimizations for single-bit $eq/$ne with constant input to opt_constClifford Wolf2013-03-19
| * improved $mux optimization in opt_constClifford Wolf2013-03-19
| * keep $mux and $_MUX_ optimizations separate in opt_constClifford Wolf2013-03-19
| * added a TODOJohann Glaser2013-03-18
| * added one more suggestion to optimize MUXes in pass "opt_const"Johann Glaser2013-03-18
| * also optimize single-bit "$mux" cells in pass "opt_const", added suggestionsJohann Glaser2013-03-18
| * fixed a crash when lines start with whitespaceJohann Glaser2013-03-18
| * added description of Makefile include files for build configurationJohann Glaser2013-03-18
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* More TODOs in READMEClifford Wolf2013-03-18
* Merge branch 'hansi'Clifford Wolf2013-03-18
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| * Removed date from auto-generated passes/techmap/stdcells.incClifford Wolf2013-03-18
| * Fixed abc eeror handlingClifford Wolf2013-03-18
| * add header to autogenerated file on its originJohann Glaser2013-03-18
| * fixed typosJohann Glaser2013-03-18
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* Fixed strerrno vs. strerror types in ABC passClifford Wolf2013-03-17
* Merge branch 'hansi'Clifford Wolf2013-03-17
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| * Cleaned up ABC file/io error handlingClifford Wolf2013-03-17
| * Set execute bit on tests/openmsp430/run-synth.sh for realClifford Wolf2013-03-17
| * added error checking at execution of ABCJohann Glaser2013-03-17
| * corrected typosJohann Glaser2013-03-17
| * set executable flags to run-synth.sh, added .gitignoreJohann Glaser2013-03-17
| * added ckeck for Icarus Verilog, otherwise the tests are silently stoppedJohann Glaser2013-03-17
| * corrected typosJohann Glaser2013-03-17
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* Fixed gcc warnings and added error handling to shell escapeClifford Wolf2013-03-15
* Added scc pass (find logic loops)Clifford Wolf2013-03-15
* Added vi .*.swp files to .gitignoreClifford Wolf2013-03-15
* Added [[CITE]] tags to abc and fsm_extract passesClifford Wolf2013-03-15
* Added additional functionality and cleanups in sigtools.h and celltypes.hClifford Wolf2013-03-15
* Changed prefix for selection operators from # to %Clifford Wolf2013-03-14
* Added #ci and #co selection operatorsClifford Wolf2013-03-14
* Added more features to #x selection operatorClifford Wolf2013-03-14
* Added "select -write" commandClifford Wolf2013-03-14
* More support code for $sr cellsClifford Wolf2013-03-14
* Added $sr cell type to celltypes.hClifford Wolf2013-03-14
* Fixed detection of public wires in opt_rmunusedClifford Wolf2013-03-10