yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
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* \|	More Makefile cleanups	Clifford Wolf	2014-02-11
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* \|	Improved "make manual" and "make clean"	Clifford Wolf	2014-02-11
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*	Improved ilang parser error messages	Clifford Wolf	2014-02-09
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*	fixed a bug in subcircuit library with cells that have connections to itself	Clifford Wolf	2014-02-09
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*	Various improvements in expose command (added -sep and -cut)	Clifford Wolf	2014-02-09
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*	Added delete {-input\|-output\|-port}	Clifford Wolf	2014-02-09
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*	Bugfix in delete command	Clifford Wolf	2014-02-09
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*	Added test cases for expose -evert-dff	Clifford Wolf	2014-02-08
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*	Fixed handling of async reset in expose -evert-dff	Clifford Wolf	2014-02-08
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*	Build fixes for log cmd	Clifford Wolf	2014-02-08
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-08
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\| *	Merge pull request #24 from hansiglaser/master	Clifford Wolf	2014-02-08
\| \|\ \| \| \| \| \| \|	added "log" command
\| \| *	added "log" command	Johann Glaser	2014-02-08
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* \|	Implemented expose -evert-dff	Clifford Wolf	2014-02-08
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* \|	Improved checking of internal cell conventions	Clifford Wolf	2014-02-08
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* \|	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	Clifford Wolf	2014-02-08
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*	Added various new options to splice command	Clifford Wolf	2014-02-08
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*	Added %a select operator	Clifford Wolf	2014-02-08
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*	Moved some passes to other source directories	Clifford Wolf	2014-02-08
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*	Added support for "keep" attribute to abc pass	Clifford Wolf	2014-02-08
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*	Added opt -purge (frontend to opt_clean -purge)	Clifford Wolf	2014-02-08
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*	Only count non-trivial attributes when findinf master signal in opt_clean	Clifford Wolf	2014-02-08
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*	Added checking for ABC modifications to Makefile and made sure we do not ↵	Clifford Wolf	2014-02-08
\| \| \| \|	have the word ERROR in regular make output
*	Now also move net labes to the right position in splice cmd	Clifford Wolf	2014-02-08
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*	Improved detection of primary wire for a signal in opt_clean	Clifford Wolf	2014-02-07
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*	Added splice command	Clifford Wolf	2014-02-07
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*	Added log_header() to splitnets	Clifford Wolf	2014-02-07
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*	Added $slice and $concat to CellTypes list	Clifford Wolf	2014-02-07
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
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*	Stronger checking of internal cells	Clifford Wolf	2014-02-07
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*	Re-enabled abc "retime" after sorting yout the yosys-bigsim problem	Clifford Wolf	2014-02-07
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*	Added echo command	Clifford Wolf	2014-02-07
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*	Fixed use of "cmd_error" in passes/cmds/design.cc	Clifford Wolf	2014-02-07
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*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06
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*	Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim ↵	Clifford Wolf	2014-02-06
\| \| \| \|	failed)
*	Updated ABC to rev 10cc13a2a0f1	Clifford Wolf	2014-02-06
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*	Added "retime" to standard ABC recipes	Clifford Wolf	2014-02-06
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*	Added copy command	Clifford Wolf	2014-02-06
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*	Added design -stash/-copy-from/-copy-to	Clifford Wolf	2014-02-06
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*	Added support for s: select expressions (wire width)	Clifford Wolf	2014-02-06
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*	Added i:, o:, and x: selection pattern	Clifford Wolf	2014-02-06
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*	Added support for %m selection op	Clifford Wolf	2014-02-06
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-06
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\| *	Merge pull request #23 from hansiglaser/master	Clifford Wolf	2014-02-06
\| \|\ \| \| \| \| \| \|	new %s: add sub-modules to selection
\| \| *	new %s: add sub-modules to selection	Johann Glaser	2014-02-06
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* /	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	Clifford Wolf	2014-02-06
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*	Added support for sat -show @<sel_name>	Clifford Wolf	2014-02-06
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*	Added sat -set-init-def and sat -tempinduct-def	Clifford Wolf	2014-02-06
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*	Added opt_const -undriven	Clifford Wolf	2014-02-06
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*	Added expose -dff	Clifford Wolf	2014-02-06
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