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* Fixed performance bug in Verific importerClifford Wolf2015-11-16
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* Changes for Verific 3.16_484_32_151112Clifford Wolf2015-11-12
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* Link to vlsitechnology.org for liberty filesClifford Wolf2015-11-12
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* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-12
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* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-11
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* Added "abc -g"Clifford Wolf2015-11-10
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* Merge pull request #97 from zeldin/masterClifford Wolf2015-11-08
|\ | | | | Fix a segfault in dffinit when the value has too few bits
| * Fix a segfault in dffinit when the value has too few bitsMarcus Comstedt2015-11-08
|/ | | | | The code was already trying to add the required number of bits, but fell one short of the mark.
* Added "singleton" passClifford Wolf2015-11-07
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* Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-06
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* Bugfix in mapping $tribuf to $_TBUF_Clifford Wolf2015-11-05
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* Bugfix in memory_dffClifford Wolf2015-10-31
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* Improvements in wreduceClifford Wolf2015-10-31
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* Bugfix in Xilinx LUT mappingClifford Wolf2015-10-30
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* Improved SigMap performanceClifford Wolf2015-10-28
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* Improvements in new SigMapClifford Wolf2015-10-28
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* Use mfp<> in equiv_markClifford Wolf2015-10-27
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* Removed old SigMap implementationClifford Wolf2015-10-27
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* Added hashlib::mfp and new SigMapClifford Wolf2015-10-27
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* Improvements in equiv_structClifford Wolf2015-10-25
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* Major refactoring of equiv_structClifford Wolf2015-10-25
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
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* Added "equiv_add -cell"Clifford Wolf2015-10-25
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* equiv_struct now creates equiv_merged attributesClifford Wolf2015-10-25
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* Improvements in equiv_structClifford Wolf2015-10-24
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* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-24
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* improvement in "stat"Clifford Wolf2015-10-24
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* Fixed driver conflict handling (various cmds)Clifford Wolf2015-10-24
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* equiv_purge bugfix, using SigChunk in Yosys namespaceClifford Wolf2015-10-24
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* Fixed handling of driver-driver conflicts in wreduceClifford Wolf2015-10-24
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* Added equiv_mark commandClifford Wolf2015-10-23
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* Disabled "Skipping blackbox module" msg in show commandClifford Wolf2015-10-23
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* Added support for ":" as comment symbol after ;-parsingClifford Wolf2015-10-23
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* Also merge $equiv cells in equiv_structClifford Wolf2015-10-23
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* Improvements in equiv_structClifford Wolf2015-10-23
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* Added equiv_purgeClifford Wolf2015-10-22
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* Added equiv_struct commandClifford Wolf2015-10-21
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* Improved inout handling in equiv_makeClifford Wolf2015-10-21
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* Progress on cell help messagesClifford Wolf2015-10-20
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* Progress on cell help messagesClifford Wolf2015-10-17
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* Progress in yosys-smtbmcClifford Wolf2015-10-15
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* Fixed bug in verilog parserClifford Wolf2015-10-15
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* Improvements in yosys-smtbmcClifford Wolf2015-10-15
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* Bugfixes in handling of "keep" attribute on wiresClifford Wolf2015-10-15
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* More "yosys-smtbmc -c" fixesClifford Wolf2015-10-14
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* Fixed yosys-smtbmc -cClifford Wolf2015-10-14
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* Added "prep" commandClifford Wolf2015-10-14
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* Added more cell descriptionsClifford Wolf2015-10-14
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* Added first help messages for cell typesClifford Wolf2015-10-14
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* Added yosys-smtbmc copyrightClifford Wolf2015-10-14
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