index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
*
Added ezSAT api support for don't care values in models
Clifford Wolf
2013-06-09
*
Fixed handling of $_XOR_ in SAT generator
Clifford Wolf
2013-06-09
*
Added sequential solving support to sat_solve
Clifford Wolf
2013-06-09
*
Set rl_basic_word_break_characters in shell
Clifford Wolf
2013-06-09
*
Improved readline tab completion
Clifford Wolf
2013-06-09
*
Look for yosys-abc and yosys-svgviewer where the main exe is
Clifford Wolf
2013-06-09
*
Added "make abc" and "make install-abc"
Clifford Wolf
2013-06-08
*
Moved cmds from kernel/ to passes/cmds/
Clifford Wolf
2013-06-08
*
Fixed typo is sat_solve help msg
Clifford Wolf
2013-06-08
*
Added support for shifter cells to SAT generator
Clifford Wolf
2013-06-08
*
Added "cd" and "ls" commands for convenience
Clifford Wolf
2013-06-08
*
Various improvements in sat_solve pass and SAT generator
Clifford Wolf
2013-06-08
*
Added -all and -max options to sat_solve
Clifford Wolf
2013-06-08
*
Fixes and improvements in ezSAT library
Clifford Wolf
2013-06-08
*
Improved auto-detection of -show signals in sat_solve
Clifford Wolf
2013-06-08
*
Improved sat generator and sat_solve pass
Clifford Wolf
2013-06-07
*
Added SAT generator and simple sat_solve command
Clifford Wolf
2013-06-07
*
Added ezSAT library
Clifford Wolf
2013-06-07
*
Renamed opt_rmunused to opt_clean
Clifford Wolf
2013-06-05
*
Implemented technology mapping for multipliers (using array multiplier)
Clifford Wolf
2013-06-03
*
Added "dump" command (part ilang backend)
Clifford Wolf
2013-06-02
*
Fixed techmap/flatten for positional module arguments
Clifford Wolf
2013-05-26
*
Improved log messages generated by hierarchy pass
Clifford Wolf
2013-05-26
*
Added -nodetect option to fsm pass
Clifford Wolf
2013-05-24
*
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
Clifford Wolf
2013-05-24
*
Improved FSM one-hot encoding, added binary encoding
Clifford Wolf
2013-05-24
*
Added log_assert() api
Clifford Wolf
2013-05-24
*
Added log_abort() api
Clifford Wolf
2013-05-24
*
Fixed a gcc vs. clang determinism problem in abc pass
Clifford Wolf
2013-05-23
*
Fixed memory corruption bug in opt_rmunused
Clifford Wolf
2013-05-23
*
Only initialize TCL interpreter when needed
Clifford Wolf
2013-05-23
*
Fixed memory leak in ilang frontend
Clifford Wolf
2013-05-23
*
Added missing newline to some error messages
Clifford Wolf
2013-05-23
*
Added labels to "help -write-tex-command-reference-manual" output
Clifford Wolf
2013-05-23
*
Added support for processes to show command
Clifford Wolf
2013-05-23
*
Fixed show command for constant assignments
Clifford Wolf
2013-05-23
*
Some improvements in opt_rmdff
Clifford Wolf
2013-05-23
*
Merge pull request #6 from hansiglaser/master
Clifford Wolf
2013-05-19
|
\
|
*
added option '-Dname[=definition]' to command 'read_verilog'
Johann Glaser
2013-05-19
|
/
*
Removed test cases that have been moved to yosys-test.
Clifford Wolf
2013-05-17
*
Fixed to aggressive x-folding in opt_const
Clifford Wolf
2013-05-17
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2013-05-16
|
\
|
*
Improved vcdcd.pl (added -d option)
Clifford Wolf
2013-05-14
*
|
Merge branch 'bugfix'
Clifford Wolf
2013-05-16
|
\
\
|
|
/
|
/
|
|
*
Fixed synthesis of functions in latched blocks
Clifford Wolf
2013-05-16
*
|
Some improvements in vcdcd.pl
Clifford Wolf
2013-05-14
*
|
Added support for verilog === operator
Clifford Wolf
2013-05-07
*
|
Added tcl "yosys -import" command
Clifford Wolf
2013-05-02
*
|
Improved/simplified TCL bindings
Clifford Wolf
2013-05-01
*
|
Added support for const cell inputs in techmap
Clifford Wolf
2013-04-27
[next]