Commit message (Expand)AuthorAge
* Improved seeding of color rng in show commandClifford Wolf2014-07-18
* Only create collision detect logic in memory_share if necessaryClifford Wolf2014-07-18
* Bugfix in tests/memories/run-test.shClifford Wolf2014-07-18
* added tests/memoriesClifford Wolf2014-07-18
* Added memory_shareClifford Wolf2014-07-18
* Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>Clifford Wolf2014-07-18
* Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN portClifford Wolf2014-07-18
* Added function-like cell creation helpersClifford Wolf2014-07-18
* Added log_id() helper functionClifford Wolf2014-07-18
* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-17
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
* Fixed simlib.v model for $memClifford Wolf2014-07-17
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
* Improved opt_reduce handling of mem wr_en mux bitsClifford Wolf2014-07-17
* Fixed RTLIL::SigSpec::append_bit() for appending constantsClifford Wolf2014-07-17
* Added support for "blackbox" attribute to iopadmapClifford Wolf2014-07-17
* Added support for "blackbox" attribute to flatten/techmapClifford Wolf2014-07-17
* Added "inout" ports support to read_libertyClifford Wolf2014-07-16
* Set blackbox attribute in "read_liberty -lib"Clifford Wolf2014-07-16
* Fixed spelling of "direction" in read_liberty messagesClifford Wolf2014-07-16
* Merged new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
| * Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
| * improved opt_reduce for $mem/$memwr WR_EN multiplexersClifford Wolf2014-07-16
| * changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
| * Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-16
| * Updated simlib to new $mem/$memwr interfaceClifford Wolf2014-07-16
| * Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-16
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-16
* Added passing of various options to vhdl2verilogClifford Wolf2014-07-12
* Use "verilog -sv" to parse .sv filesClifford Wolf2014-07-11
* Fixed processing of initial values for block-local variablesClifford Wolf2014-07-11
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-05
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
* small changes in presentationClifford Wolf2014-07-02
* Tiny fix in presentationClifford Wolf2014-06-29
* Progress in presentationClifford Wolf2014-06-29
* Added links to some liberty files to READMEClifford Wolf2014-06-28
* Progress in presentationClifford Wolf2014-06-26
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
* More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-24
* Progress in presentationClifford Wolf2014-06-22
* Little steps in realmath test benchClifford Wolf2014-06-21
* fixed signdness detection for expressions with realsClifford Wolf2014-06-21
* fixed typoClifford Wolf2014-06-21
* Progress in presentationClifford Wolf2014-06-21
* Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-19
* Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Improved handling of relational op of real valuesClifford Wolf2014-06-17