yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Improved seeding of color rng in show command	Clifford Wolf	2014-07-18
*	Only create collision detect logic in memory_share if necessary	Clifford Wolf	2014-07-18
*	Bugfix in tests/memories/run-test.sh	Clifford Wolf	2014-07-18
*	added tests/memories	Clifford Wolf	2014-07-18
*	Added memory_share	Clifford Wolf	2014-07-18
*	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	Clifford Wolf	2014-07-18
*	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	Clifford Wolf	2014-07-18
*	Added function-like cell creation helpers	Clifford Wolf	2014-07-18
*	Added log_id() helper function	Clifford Wolf	2014-07-18
*	Also simulate unmapped memories in "make test"	Clifford Wolf	2014-07-17
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17
*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17
*	Improved opt_reduce handling of mem wr_en mux bits	Clifford Wolf	2014-07-17
*	Fixed RTLIL::SigSpec::append_bit() for appending constants	Clifford Wolf	2014-07-17
*	Added support for "blackbox" attribute to iopadmap	Clifford Wolf	2014-07-17
*	Added support for "blackbox" attribute to flatten/techmap	Clifford Wolf	2014-07-17
*	Added "inout" ports support to read_liberty	Clifford Wolf	2014-07-16
*	Set blackbox attribute in "read_liberty -lib"	Clifford Wolf	2014-07-16
*	Fixed spelling of "direction" in read_liberty messages	Clifford Wolf	2014-07-16
*	Merged new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
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\| *	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
\| *	improved opt_reduce for $mem/$memwr WR_EN multiplexers	Clifford Wolf	2014-07-16
\| *	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
\| *	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16
\| *	Updated simlib to new $mem/$memwr interface	Clifford Wolf	2014-07-16
\| *	Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal	Clifford Wolf	2014-07-16
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*	Added note to "make test": use git checkout of iverilog	Clifford Wolf	2014-07-16
*	Added passing of various options to vhdl2verilog	Clifford Wolf	2014-07-12
*	Use "verilog -sv" to parse .sv files	Clifford Wolf	2014-07-11
*	Fixed processing of initial values for block-local variables	Clifford Wolf	2014-07-11
*	now ignore init attributes on non-register wires in sat command	Clifford Wolf	2014-07-05
*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02
*	small changes in presentation	Clifford Wolf	2014-07-02
*	Tiny fix in presentation	Clifford Wolf	2014-06-29
*	Progress in presentation	Clifford Wolf	2014-06-29
*	Added links to some liberty files to README	Clifford Wolf	2014-06-28
*	Progress in presentation	Clifford Wolf	2014-06-26
*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25
*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24
*	Progress in presentation	Clifford Wolf	2014-06-22
*	Little steps in realmath test bench	Clifford Wolf	2014-06-21
*	fixed signdness detection for expressions with reals	Clifford Wolf	2014-06-21
*	fixed typo	Clifford Wolf	2014-06-21
*	Progress in presentation	Clifford Wolf	2014-06-21
*	Do not create $dffsr cells with no-op resets in proc_dff	Clifford Wolf	2014-06-19
*	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17
*	Added AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17
*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17