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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
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* Replaced "#ifdef WIN32" with "#ifdef _WIN32"Clifford Wolf2014-10-09
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* Added API for generic cell cost calculationsClifford Wolf2014-10-09
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* added .exe and .html output files to .gitignoreClifford Wolf2014-10-09
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* No rusage on win32Clifford Wolf2014-10-09
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* Added mxe-based cross build for win32Clifford Wolf2014-10-09
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* Fixes in "hilomap" help messageClifford Wolf2014-10-08
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* sort cell types in "stat" output by nameClifford Wolf2014-10-03
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* sat encoding for exclusive $pmux ctrl inputs in "share" passClifford Wolf2014-10-03
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* satgen import sigbit apiClifford Wolf2014-10-03
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* added resource sharing of $macc cellsClifford Wolf2014-10-03
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* Added $_BUF_ cell typeClifford Wolf2014-10-03
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* remove buffers in opt_cleanClifford Wolf2014-10-03
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* resource sharing of $alu cellsClifford Wolf2014-10-03
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* set "keep" on modules with $assert cells in "hierarchy"Clifford Wolf2014-09-30
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* Added support for "keep" on modulesClifford Wolf2014-09-29
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* namespace YosysClifford Wolf2014-09-27
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* Merge pull request #39 from ahmedirfan1983/masterClifford Wolf2014-09-22
|\ | | | | merged with current mas.ter branch + features added + bug fixes
| * Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-22
| |\ | |/ |/| | | | | | | | | | | | | added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
* | Re-enabled assert for new logic loops in "share" passClifford Wolf2014-09-21
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* | Various improvements regarding logic loops in "share" resultsClifford Wolf2014-09-21
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* | Logic loop bugfix for "share" passClifford Wolf2014-09-21
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* | Added "share -limit"Clifford Wolf2014-09-21
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* | Still loop bug in "share": changed assert to warningClifford Wolf2014-09-21
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* | Do not introduce new logic loops in "share"Clifford Wolf2014-09-21
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* | Assert on new logic loops in "share" passClifford Wolf2014-09-21
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* | Added "test_abcloop" commandClifford Wolf2014-09-19
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* | Initialize RTLIL::Const from std::vector<bool>Clifford Wolf2014-09-19
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* | Sorting of object names in ilang backendClifford Wolf2014-09-19
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* | Small improvements in "abc" command handle_loops() functionClifford Wolf2014-09-19
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* | Using "NOT" instead of "INV" as cell name in default abc genlib fileClifford Wolf2014-09-19
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* | Alphabetically sort port names in "show" outputClifford Wolf2014-09-19
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* | Do not run "scorr" in "abc -fast"Clifford Wolf2014-09-18
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* | Improvements in "synth" scriptClifford Wolf2014-09-18
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* | Added "abc -fast"Clifford Wolf2014-09-18
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* | Added commit count to devel version numberClifford Wolf2014-09-17
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* | Fixed $_NOR vs. $_NOR_ typo in abc.ccClifford Wolf2014-09-16
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* | Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-16
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* | Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)Clifford Wolf2014-09-16
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* | Fixed $macc simlib model for zero-configClifford Wolf2014-09-16
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* | More aggressive $macc merging in alumaccClifford Wolf2014-09-15
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* | Added the obvious optimizations to alumacc $macc generatorClifford Wolf2014-09-15
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* | Improved maccmap tree bit packingClifford Wolf2014-09-15
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* | Fixed wreduce $shiftx handlingClifford Wolf2014-09-15
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* | Fixed monitor notifications for removed cellClifford Wolf2014-09-14
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* | Added "synth" commandClifford Wolf2014-09-14
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* | Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-14
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* | Using alumacc in techmap.vClifford Wolf2014-09-14
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* | Various fixes/cleanups in alumacc and maccmapClifford Wolf2014-09-14
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* | Added techmap_wrap attributeClifford Wolf2014-09-14
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