yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
...
*	New interface for $__alu in techmap.v	Clifford Wolf	2014-08-13
*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13
*	Fixed handling of constant-true branches in proc_clean	Clifford Wolf	2014-08-12
*	Added test_verific mode to tests/fsm/generate.py	Clifford Wolf	2014-08-12
*	Fixed SigBit(RTLIL::Wire *wire) constructor	Clifford Wolf	2014-08-12
*	Fixed building verific bindings	Clifford Wolf	2014-08-12
*	Added multi-dim memory test (requires iverilog git head)	Clifford Wolf	2014-08-12
*	Another build fix by americanrouter (via reddit)	Clifford Wolf	2014-08-11
*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10
*	Fixed "share" for complex scenarios with never-active cells	Clifford Wolf	2014-08-09
*	Do not share any $reduce_* cells (its complicated and not worth it anyways)	Clifford Wolf	2014-08-09
*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09
*	Improved FSM tests	Clifford Wolf	2014-08-08
*	Another fsm_extract bugfix	Clifford Wolf	2014-08-08
*	Fixed "fsm -export"	Clifford Wolf	2014-08-08
*	Fixed sharing of reduce operator	Clifford Wolf	2014-08-08
*	Fixed fsm_extract for wreduced muxes	Clifford Wolf	2014-08-08
*	Added FSM test bench	Clifford Wolf	2014-08-08
*	Added "sat -prove-skip"	Clifford Wolf	2014-08-08
*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07
*	Use "-keepdc" in "miter -equiv -flatten"	Clifford Wolf	2014-08-07
*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07
*	Added adff2dff.v (for techmap -share_map)	Clifford Wolf	2014-08-07
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06
*	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05
*	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05
*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05
*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05
*	Added mux support to wreduce command	Clifford Wolf	2014-08-05
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05
*	Added "show -signed"	Clifford Wolf	2014-08-04
*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04
*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04
*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03
*	Added "wreduce" to some of the standard test benches	Clifford Wolf	2014-08-03
*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03
*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03
*	Added query() API to ModIndex	Clifford Wolf	2014-08-03
*	Added ID() macro for static IdStrings	Clifford Wolf	2014-08-03
*	Implemented recursive techmap	Clifford Wolf	2014-08-03
*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03
*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02
*	Fixed a va_list corruption in logv_error()	Clifford Wolf	2014-08-02
*	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02
*	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02
*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02
*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02