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* Fixed memory leak in DPI function callsClifford Wolf2014-08-21
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-08-21
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| * Added mod->addGate() methods for new gate typesClifford Wolf2014-08-19
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* | Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
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* | Added support for global tasks and functionsClifford Wolf2014-08-21
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* Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-18
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* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-18
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* Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-18
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* Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-18
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* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-18
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* Fixed proc_{self,share}_dirname error handlingClifford Wolf2014-08-17
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* Makefile fixesClifford Wolf2014-08-17
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* Improved AST ProcessGenerator performanceClifford Wolf2014-08-17
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* Improved sig.remove2() performanceClifford Wolf2014-08-17
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* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-17
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* Added stackmap<> containerClifford Wolf2014-08-17
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* Renamed toposort.h to utils.hClifford Wolf2014-08-17
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* Added module->uniquify()Clifford Wolf2014-08-16
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* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-16
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* Multiply using a carry-save accumulatorClifford Wolf2014-08-16
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* Added "test_cell -s <seed>"Clifford Wolf2014-08-16
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* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-16
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-16
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* Added CellTypes::cell_evaluable()Clifford Wolf2014-08-16
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* Changes in techmap $__alu interfaceClifford Wolf2014-08-16
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* Added "opt -fast"Clifford Wolf2014-08-16
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* Added log_spacer()Clifford Wolf2014-08-16
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* Bugfix in iopadmapClifford Wolf2014-08-15
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* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
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* Removed old doc references to $safe_pmuxClifford Wolf2014-08-15
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* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
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* Added Frontend "+/" filename syntax for files from proc_share_dirClifford Wolf2014-08-15
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* document "techmap -map %<design-name>"Clifford Wolf2014-08-15
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* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-15
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* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
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* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
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* Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-14
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* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-14
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* Fixed handling of task outputsClifford Wolf2014-08-14
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* Simplified $__arraymul techmap ruleClifford Wolf2014-08-14
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* Added module->portsClifford Wolf2014-08-14
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* Refactoring of CellType classClifford Wolf2014-08-14
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* RIP $safe_pmuxClifford Wolf2014-08-14
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* Some improvements in FSM mapping and recodingClifford Wolf2014-08-14
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* Added "abc -D" for setting delay targetClifford Wolf2014-08-14
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* Updated ABC to 4935c2b946deClifford Wolf2014-08-14
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* Added techmap support for actual lookahead carry unitClifford Wolf2014-08-13
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* Preparations for lookahead ALU support in techmap.vClifford Wolf2014-08-13
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* Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-13
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