Commit message (Expand)AuthorAge
* Squashed commit of the following:Ruben Undheim2016-09-23
* We are now in 0.6+ developmentClifford Wolf2016-02-26
* Yosys 0.6Clifford Wolf2016-02-26
* Fixed BLIF parser for empty port assignmentsClifford Wolf2016-02-24
* Use easyer-to-read unoptimized ceil_log2()Clifford Wolf2016-02-15
* Updated ABC to ae7d65e71adcClifford Wolf2016-02-15
* Updated command reference in manualClifford Wolf2016-02-14
* Changelog for upcoming 0.6 releaseClifford Wolf2016-02-14
* Fixed more visual studio warningsClifford Wolf2016-02-14
* Fixed some visual studio warningsClifford Wolf2016-02-13
* Merge branch 'master' of Wolf2016-02-13
| * Fixed MXE ABC buildClifford Wolf2016-02-13
* | Added "int ceil_log2(int)" functionClifford Wolf2016-02-13
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-13
* Support for more Verific primitives (patch I got per email)Clifford Wolf2016-02-13
* Updated ABCClifford Wolf2016-02-08
* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-07
* Updated ABCClifford Wolf2016-02-07
* Added "stat -liberty" for calculating chip areaClifford Wolf2016-02-04
* Bugfix in Verific front-endClifford Wolf2016-02-03
* Updated verific build instructionsClifford Wolf2016-02-02
* Improved dffsr2dff passClifford Wolf2016-02-02
* Added dffsr2dffClifford Wolf2016-02-02
* Added addBufGate module methodClifford Wolf2016-02-02
* Use alphanumerical order instead of idstring idx in opt_clean compare_signals()Clifford Wolf2016-02-02
* Added CodeOfConductClifford Wolf2016-02-01
* Updated ABC to hg rev ee212a9e94dfClifford Wolf2016-02-01
* Progress in cell library documentationClifford Wolf2016-02-01
* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-01
* Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)Clifford Wolf2016-02-01
* SigMap performance improvementClifford Wolf2016-02-01
* hashlib mfp<> performance improvementsClifford Wolf2016-02-01
* Added reserve() method to haslib classes andClifford Wolf2016-01-31
* Merge branch 'rtlil_remove2_speedup' of Wolf2016-01-31
| * rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)Rick Altherr2016-01-31
| * rtlil: speed up SigSpec::sort_and_unify()Rick Altherr2016-01-31
| * rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)Rick Altherr2016-01-31
| * genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...Rick Altherr2016-01-31
| * rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)Rick Altherr2016-01-31
* | More clang sanitizer stuffClifford Wolf2016-01-31
* Meaningless coding style changeClifford Wolf2016-01-31
* Merge branch 'rtlil_remove2_speedup' of Wolf2016-01-31
| * rtlil: rewrite remove2() to avoid copyingRick Altherr2016-01-30
| * rtlil: duplicate remove2() for std::set<>Rick Altherr2016-01-29
| * rtlil: change IdString comparison operators to take references instead of copiesRick Altherr2016-01-29
* | Addedd clang sanitizersClifford Wolf2016-01-31
* Added "equiv_struct -fwonly"Clifford Wolf2016-01-08
* Bugfixes in equiv_structClifford Wolf2016-01-08
* Added "submod -copy"Clifford Wolf2016-01-08
* Added "write_blif -cname" modeClifford Wolf2016-01-06