Commit message (Expand)AuthorAge
| * Fixed "make clean" for out-of-tree buildsClifford Wolf2015-08-12
| * Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
| * Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-12
| * Fixed hashlib for 64 bit int keysClifford Wolf2015-08-12
| * Added SMV back-end '' scriptClifford Wolf2015-08-12
* | More ASCII encoding fixesClifford Wolf2015-08-13
* | Fixed CRLF line endingsClifford Wolf2015-08-13
* | Some ASCII encoding fixes (comments and docs) by Larry DoolittleClifford Wolf2015-08-13
* Merge pull request #70 from gaomy3832/bugfixClifford Wolf2015-08-12
| * Remove unused blackbox modules in opt_clean.Mingyu Gao2015-08-11
| * Bugfix for cell hash cache option in opt_share.Mingyu Gao2015-08-10
* | Bugfix for cell hash cache option in opt_share.Mingyu Gao2015-08-11
* | Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-11
* | Added missing ct_all setup to opt_cleanClifford Wolf2015-08-11
* Use MEMID as name for $mem cellClifford Wolf2015-08-09
* Merge pull request #69 from zeldin/masterClifford Wolf2015-08-07
| * Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-06
* Remove some very strange whitespace in (by Larry Doolittle)Clifford Wolf2015-08-05
* Bugfix in SMV back-end for partially unassigned wiresClifford Wolf2015-08-05
* Added ENABLE_LIBYOSYS Makefile optionClifford Wolf2015-08-04
* Added $assert support to SMV back-endClifford Wolf2015-08-04
* Added buildClifford Wolf2015-08-04
* Merge pull request #68 from zeldin/masterClifford Wolf2015-08-01
| * Add -noautowire option to verilog frontendMarcus Comstedt2015-08-01
* Added WORDS parameter to $meminitClifford Wolf2015-07-31
* Fixed flatten $meminit handlingClifford Wolf2015-07-30
* Improvements in BLIF back-endClifford Wolf2015-07-29
* Fixed nested mem2regClifford Wolf2015-07-29
* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-27
* Fixed "check" command for inout portsClifford Wolf2015-07-27
* Some cleanups in opt_rmdffClifford Wolf2015-07-25
* Added "miter -assert"Clifford Wolf2015-07-25
* Keep modules with $assume (like $assert)Clifford Wolf2015-07-25
* Improved $adff simplificationClifford Wolf2015-07-24
* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-20
* Fixed techmap processes error msgClifford Wolf2015-07-18
* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-18
* Some fixes in "select" commandClifford Wolf2015-07-16
* Fixed YosysJS.create_worker() usage of this.url_prefixClifford Wolf2015-07-10
* Improved liberty file test caseClifford Wolf2015-07-06
* Updated ABCClifford Wolf2015-07-06
* Do not collect disabled $memwr cellsClifford Wolf2015-07-06
* Improved YosysJS WebWorker APIClifford Wolf2015-07-04
* Bugfix in fsm_extractClifford Wolf2015-07-03
* Added "synth -nofsm"Clifford Wolf2015-07-02
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added opt_const -clkinvClifford Wolf2015-07-01
* Added logic-loop error handling to freduceClifford Wolf2015-06-30
* Merge branch 'master' of Wolf2015-06-30
| * Added YosysJS.create_worker()Clifford Wolf2015-06-28