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* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
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* Improved way of connecting ports in techmap passClifford Wolf2013-10-17
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* Only prefer connected signals iff they have public namesClifford Wolf2013-10-17
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* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-17
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* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-17
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* Avoid re-arranging signals on register outputsClifford Wolf2013-10-17
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* Fixed detection of major wires in opt_cleanClifford Wolf2013-10-17
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* Added iopadmap passClifford Wolf2013-10-16
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* Moved dfflibmap from passes/dfflibmap to passes/techmapClifford Wolf2013-10-16
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* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-16
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* Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'Clifford Wolf2013-10-16
| | | | Patch by Tim Edwards
* Added recommended apt-get commands to READMEClifford Wolf2013-10-11
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* Fixed minisat includeClifford Wolf2013-10-11
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* Pinned ABC revision to 0f9e5488ced3Clifford Wolf2013-10-03
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* Improvements in EDIF backendClifford Wolf2013-09-17
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* Added additional options to BLIF backendClifford Wolf2013-09-15
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* Added BLIF backendClifford Wolf2013-09-15
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* A couple of small fixes in SPICE backendClifford Wolf2013-09-15
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
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* Updated manualClifford Wolf2013-09-15
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* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
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* Added spice backendClifford Wolf2013-09-14
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-09-03
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| * Encode large (>32 bits) parameters as hex string in edif backendClifford Wolf2013-08-28
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| * Improved edif backendClifford Wolf2013-08-27
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| * Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-27
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* | Added -selected option to various backendsClifford Wolf2013-09-03
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* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-22
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* More explicit integer output in verilog backendClifford Wolf2013-08-22
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* Added correct encoding of identifiers in EDIF backendClifford Wolf2013-08-22
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* Added edif backend (still under construction)Clifford Wolf2013-08-22
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* Merge pull request #10 from hansiglaser/masterClifford Wolf2013-08-21
|\ | | | | fixed Verilog parser filename and line numbering issue with include files
| * fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-21
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* | Some minor documentation fixesClifford Wolf2013-08-21
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* | Merge pull request #9 from hansiglaser/masterClifford Wolf2013-08-20
|\ \ | |/ | | Added support for include directories with the new '-I' argument of the 'read_verilog' command
| * Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-20
| | | | | | | | 'read_verilog' command
* | Merge pull request #8 from hansiglaser/masterClifford Wolf2013-08-20
|\ \ | |/ | | Added support for notif0/notif1 primitives
| * Added support for notif0/notif1 primitivesJohann Glaser2013-08-20
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* Added cleaning of old version_* files to version_* make ruleClifford Wolf2013-08-20
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* Added version info to yosys command and added -V optionClifford Wolf2013-08-20
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* Minor fixes in abc build instructions and abc passClifford Wolf2013-08-20
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* Fixed width and sign detection for ** operatorClifford Wolf2013-08-19
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* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-19
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* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
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* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-15
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* Fixed signed div/mod in const eval (rounding and stuff)Clifford Wolf2013-08-15
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* Added ezsat api for creation of anonymous vectorsClifford Wolf2013-08-15
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* Added sat -ignore_div_by_zero switchClifford Wolf2013-08-15
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* Added eval -brute_force_equiv_checker_x modeClifford Wolf2013-08-15
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* Added support for "2**n" shifter encodingClifford Wolf2013-08-12
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