| Commit message (Collapse) | Author | Age |
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Fixed bug in $mem cell verilog code generation.
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Added support for $mem cells in the verilog backend.
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Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
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write-enable bits and RD_TRANSPARENT parameter settings.
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based on a patch by Mingyu Gao, user gaomy3832 on github
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