yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09
\|\
\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09
\|/
*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07
*	Removed tests/xsthammer	Clifford Wolf	2013-07-07
*	Added opt_clean -purge option	Clifford Wolf	2013-07-07
*	Fixed handling of $eq and $ne in opt_const	Clifford Wolf	2013-07-07
*	Fixed vivado related xsthammer bugs	Clifford Wolf	2013-07-05
*	Various improvements in xsthammer report generator	Clifford Wolf	2013-07-05
*	Added work-around to isim bug in xsthammer report script	Clifford Wolf	2013-07-05
*	Fixed gcc warnings in ezminisat	Clifford Wolf	2013-07-05
*	Added CARRY4 Xilinx cell to xsthammer cell lib	Clifford Wolf	2013-07-05
*	Added xsthammer report generator	Clifford Wolf	2013-07-05
*	Improved xsthammer quartus support	Clifford Wolf	2013-07-04
*	Added Altera Cyclon III cell library to xsthammer	Clifford Wolf	2013-07-04
*	Documentation updates	Clifford Wolf	2013-07-04
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
*	Added QMAKE makefile variable	Clifford Wolf	2013-07-03
*	Added Altera Quartus support to xsthammer	Clifford Wolf	2013-07-03
*	Progress in xsthammer	Clifford Wolf	2013-07-03
*	Added vivado support to xsthammer	Clifford Wolf	2013-06-26
*	Added SAT support for -all/-max with -verify	Clifford Wolf	2013-06-23
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-06-20
\|\
\| *	Added renaming of wires and cells to "rename" command	Clifford Wolf	2013-06-19
* \|	Added timout functionality to SAT solver	Clifford Wolf	2013-06-20
\|/
*	Added "eval" pass	Clifford Wolf	2013-06-19
*	Fixed build with clang	Clifford Wolf	2013-06-18
*	Added splitnets command	Clifford Wolf	2013-06-18
*	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	Clifford Wolf	2013-06-18
*	Added more stuff to xsthammer, found first xst bug	Clifford Wolf	2013-06-17
*	Added support for "assign" statements in abc vlparse	Clifford Wolf	2013-06-15
*	Added ternary op and concat op to xsthammer	Clifford Wolf	2013-06-15
*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14
*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13
*	More xsthammer improvements (using xst 14.5 now)	Clifford Wolf	2013-06-13
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-06-12
\|\
\| *	Added "scatter" command	Clifford Wolf	2013-06-12
\| *	Renamed yosys-show temp files to be dot-files in the users home directory	Clifford Wolf	2013-06-12
\| *	Fixed gcc build (c++11 stuff in ezSAT)	Clifford Wolf	2013-06-12
* \|	Another fix for a bug found using xsthammer	Clifford Wolf	2013-06-12
\|/
*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11
*	More xsthammer improvements	Clifford Wolf	2013-06-10
*	More sign-extension related fixes	Clifford Wolf	2013-06-10
*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10
*	Progress xsthammer scripts	Clifford Wolf	2013-06-10
*	Improvements and fixes in SAT code	Clifford Wolf	2013-06-10
*	Added history file read/write to driver	Clifford Wolf	2013-06-10
*	Progress in xsthammer: working proof for cell models	Clifford Wolf	2013-06-10