Commit message (Expand)AuthorAge
* Fixes and improvements in AST const foldingClifford Wolf2013-06-10
* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
* Fixed generation of newlines in "dump" outputClifford Wolf2013-06-10
* Added "rename" commandClifford Wolf2013-06-10
* Progress on xsthammerClifford Wolf2013-06-10
* Added first xsthammer scriptsClifford Wolf2013-06-10
* Renamed "sat_solve" pass to "sat"Clifford Wolf2013-06-09
* Implemented temporal induction proofs in sat_solveClifford Wolf2013-06-09
* Added support for non-temporal proofs to sat_solveClifford Wolf2013-06-09
* Re-organization in sat_solver pass for temporal inductionClifford Wolf2013-06-09
* Added ezSAT api support for don't care values in modelsClifford Wolf2013-06-09
* Fixed handling of $_XOR_ in SAT generatorClifford Wolf2013-06-09
* Added sequential solving support to sat_solveClifford Wolf2013-06-09
* Set rl_basic_word_break_characters in shellClifford Wolf2013-06-09
* Improved readline tab completionClifford Wolf2013-06-09
* Look for yosys-abc and yosys-svgviewer where the main exe isClifford Wolf2013-06-09
* Added "make abc" and "make install-abc"Clifford Wolf2013-06-08
* Moved cmds from kernel/ to passes/cmds/Clifford Wolf2013-06-08
* Fixed typo is sat_solve help msgClifford Wolf2013-06-08
* Added support for shifter cells to SAT generatorClifford Wolf2013-06-08
* Added "cd" and "ls" commands for convenienceClifford Wolf2013-06-08
* Various improvements in sat_solve pass and SAT generatorClifford Wolf2013-06-08
* Added -all and -max options to sat_solveClifford Wolf2013-06-08
* Fixes and improvements in ezSAT libraryClifford Wolf2013-06-08
* Improved auto-detection of -show signals in sat_solveClifford Wolf2013-06-08
* Improved sat generator and sat_solve passClifford Wolf2013-06-07
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
* Added ezSAT libraryClifford Wolf2013-06-07
* Renamed opt_rmunused to opt_cleanClifford Wolf2013-06-05
* Implemented technology mapping for multipliers (using array multiplier)Clifford Wolf2013-06-03
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-02
* Fixed techmap/flatten for positional module argumentsClifford Wolf2013-05-26
* Improved log messages generated by hierarchy passClifford Wolf2013-05-26
* Added -nodetect option to fsm passClifford Wolf2013-05-24
* Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.vClifford Wolf2013-05-24
* Improved FSM one-hot encoding, added binary encodingClifford Wolf2013-05-24
* Added log_assert() apiClifford Wolf2013-05-24
* Added log_abort() apiClifford Wolf2013-05-24
* Fixed a gcc vs. clang determinism problem in abc passClifford Wolf2013-05-23
* Fixed memory corruption bug in opt_rmunusedClifford Wolf2013-05-23
* Only initialize TCL interpreter when neededClifford Wolf2013-05-23
* Fixed memory leak in ilang frontendClifford Wolf2013-05-23
* Added missing newline to some error messagesClifford Wolf2013-05-23
* Added labels to "help -write-tex-command-reference-manual" outputClifford Wolf2013-05-23
* Added support for processes to show commandClifford Wolf2013-05-23
* Fixed show command for constant assignmentsClifford Wolf2013-05-23
* Some improvements in opt_rmdffClifford Wolf2013-05-23
* Merge pull request #6 from hansiglaser/masterClifford Wolf2013-05-19
| * added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-19
* Removed test cases that have been moved to yosys-test.Clifford Wolf2013-05-17