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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-07-09
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| * Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
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* | Fixed shift ops with large right hand sideClifford Wolf2013-07-09
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* Fixed another bug found using vloghammerClifford Wolf2013-07-07
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* Fixed AST_CONSTANT node generationClifford Wolf2013-07-07
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* Removed tests/xsthammerClifford Wolf2013-07-07
| | | | | This test is now available as 'vloghammer' in a seperate repository: https://github.com/cliffordwolf/VlogHammer
* Added opt_clean -purge optionClifford Wolf2013-07-07
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* Fixed handling of $eq and $ne in opt_constClifford Wolf2013-07-07
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* Fixed vivado related xsthammer bugsClifford Wolf2013-07-05
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* Various improvements in xsthammer report generatorClifford Wolf2013-07-05
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* Added work-around to isim bug in xsthammer report scriptClifford Wolf2013-07-05
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* Fixed gcc warnings in ezminisatClifford Wolf2013-07-05
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* Added CARRY4 Xilinx cell to xsthammer cell libClifford Wolf2013-07-05
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* Added xsthammer report generatorClifford Wolf2013-07-05
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* Improved xsthammer quartus supportClifford Wolf2013-07-04
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* Added Altera Cyclon III cell library to xsthammerClifford Wolf2013-07-04
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* Documentation updatesClifford Wolf2013-07-04
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* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
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* Added QMAKE makefile variableClifford Wolf2013-07-03
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* Added Altera Quartus support to xsthammerClifford Wolf2013-07-03
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* Progress in xsthammerClifford Wolf2013-07-03
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* Added vivado support to xsthammerClifford Wolf2013-06-26
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* Added SAT support for -all/-max with -verifyClifford Wolf2013-06-23
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-06-20
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| * Added renaming of wires and cells to "rename" commandClifford Wolf2013-06-19
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* | Added timout functionality to SAT solverClifford Wolf2013-06-20
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* Added "eval" passClifford Wolf2013-06-19
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* Fixed build with clangClifford Wolf2013-06-18
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* Added splitnets commandClifford Wolf2013-06-18
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* Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() APIClifford Wolf2013-06-18
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* Added more stuff to xsthammer, found first xst bugClifford Wolf2013-06-17
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* Added support for "assign" statements in abc vlparseClifford Wolf2013-06-15
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* Added ternary op and concat op to xsthammerClifford Wolf2013-06-15
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* Fixed even more ConstEval bugs found using xsthammerClifford Wolf2013-06-14
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* Added consteval testing to xsthammer and fixed bugsClifford Wolf2013-06-13
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* More xsthammer improvements (using xst 14.5 now)Clifford Wolf2013-06-13
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* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-06-12
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| * Added "scatter" commandClifford Wolf2013-06-12
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| * Renamed yosys-show temp files to be dot-files in the users home directoryClifford Wolf2013-06-12
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| * Fixed gcc build (c++11 stuff in ezSAT)Clifford Wolf2013-06-12
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* | Another fix for a bug found using xsthammerClifford Wolf2013-06-12
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* Further improved and extended xsthammerClifford Wolf2013-06-11
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* More xsthammer improvementsClifford Wolf2013-06-10
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* More sign-extension related fixesClifford Wolf2013-06-10
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* Sign-extension related fixes in SatGen and AST frontendClifford Wolf2013-06-10
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* Progress xsthammer scriptsClifford Wolf2013-06-10
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* Improvements and fixes in SAT codeClifford Wolf2013-06-10
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* Added history file read/write to driverClifford Wolf2013-06-10
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* Progress in xsthammer: working proof for cell modelsClifford Wolf2013-06-10
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