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* Added mapping of synchronous set/reset to iCE40 flowClifford Wolf2015-04-17
* Improved "maccmap" help messageClifford Wolf2015-04-16
* A "#" does start a comment, not a label.Clifford Wolf2015-04-16
* Changed ice40 ICESTORM_CARRYCONST port nameClifford Wolf2015-04-16
* Fixed "dff2dffe -direct-match"Clifford Wolf2015-04-16
* Added simple ice40 dff testsClifford Wolf2015-04-16
* improved ice40 dff cell mappingClifford Wolf2015-04-16
* Added "dff2dffe -direct-match"Clifford Wolf2015-04-16
* use "hierarchy -auto-top" in synth_ice40Clifford Wolf2015-04-14
* more cells in ice40 cell libraryClifford Wolf2015-04-14
* Added "splice -wires"Clifford Wolf2015-04-13
* Added handling of bool-output cells to "wreduce"Clifford Wolf2015-04-13
* Improved xilinx "bram1" testClifford Wolf2015-04-09
* Added memory_bram "make_outreg" featureClifford Wolf2015-04-09
* Added back-end auto-detect for .edif and .jsonClifford Wolf2015-04-09
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-09
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-09
* Fixed const2big performance bugClifford Wolf2015-04-09
* techmap code cleanupClifford Wolf2015-04-09
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-09
* Added support for "file names with blanks"Clifford Wolf2015-04-08
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-08
* Added %M and %C select operatorsClifford Wolf2015-04-07
* Added "pmuxtree" commandClifford Wolf2015-04-07
* Added "chparam -list"Clifford Wolf2015-04-07
* Added decoder generation to "muxcover"Clifford Wolf2015-04-07
* Added hashlib support for std::tuple<>Clifford Wolf2015-04-07
* Added "muxcover" commandClifford Wolf2015-04-07
* Added pool<K>::pop()Clifford Wolf2015-04-07
* typo fixClifford Wolf2015-04-07
* Added "chparam" commandClifford Wolf2015-04-07
* Added support for initialized xilinx bramsClifford Wolf2015-04-06
* Added support for initialized bramsClifford Wolf2015-04-06
* Added Xilinx test case for initialized bramsClifford Wolf2015-04-06
* Added Xilinx bram black-box modulesClifford Wolf2015-04-06
* Added "port_directions" to write_json outputClifford Wolf2015-04-06
* Avoid parameter values with size 0 ($mem cells)Clifford Wolf2015-04-05
* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-05
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-05
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-04
* Added "init" attribute support to verilog backendClifford Wolf2015-04-04
* appnote 012 fixClifford Wolf2015-04-04
* Appnote 012Clifford Wolf2015-04-04
* Updated ABC to 51705b168d7aClifford Wolf2015-04-04
* Merge pull request #55 from ahmedirfan1983/masterClifford Wolf2015-04-04
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| * Update READMEAhmed Irfan2015-04-03
| * Delete btor.ysAhmed Irfan2015-04-03
| * Update READMEAhmed Irfan2015-04-03
| * separated memory next from write cellAhmed Irfan2015-04-03
| * Merge branch 'master' of https://github.com/cliffordwolf/yosysAhmed Irfan2015-04-03
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