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Debian dgit repo for package yosys
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Age
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Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Clifford Wolf
2014-07-16
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Added note to "make test": use git checkout of iverilog
Clifford Wolf
2014-07-16
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Added passing of various options to vhdl2verilog
Clifford Wolf
2014-07-12
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Use "verilog -sv" to parse .sv files
Clifford Wolf
2014-07-11
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Fixed processing of initial values for block-local variables
Clifford Wolf
2014-07-11
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now ignore init attributes on non-register wires in sat command
Clifford Wolf
2014-07-05
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fixed parsing of constant with comment between size and value
Clifford Wolf
2014-07-02
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small changes in presentation
Clifford Wolf
2014-07-02
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Tiny fix in presentation
Clifford Wolf
2014-06-29
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Progress in presentation
Clifford Wolf
2014-06-29
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Added links to some liberty files to README
Clifford Wolf
2014-06-28
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Progress in presentation
Clifford Wolf
2014-06-26
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Fixed handling of mixed real/int ternary expressions
Clifford Wolf
2014-06-25
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More found_real-related fixes to AstNode::detectSignWidthWorker
Clifford Wolf
2014-06-24
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Progress in presentation
Clifford Wolf
2014-06-22
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Little steps in realmath test bench
Clifford Wolf
2014-06-21
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fixed signdness detection for expressions with reals
Clifford Wolf
2014-06-21
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fixed typo
Clifford Wolf
2014-06-21
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Progress in presentation
Clifford Wolf
2014-06-21
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Do not create $dffsr cells with no-op resets in proc_dff
Clifford Wolf
2014-06-19
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Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf
2014-06-17
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Added AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf
2014-06-17
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Improved handling of relational op of real values
Clifford Wolf
2014-06-17
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Little steps in realmath test bench
Clifford Wolf
2014-06-16
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Improved ternary support for real values
Clifford Wolf
2014-06-16
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Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
Clifford Wolf
2014-06-16
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Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
Clifford Wolf
2014-06-16
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Added found_real feature to AstNode::detectSignWidth
Clifford Wolf
2014-06-16
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Added more calls to "hierarchy" to README file
Clifford Wolf
2014-06-15
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Removed long running tests from tests/simple/realexpr.v (replaced by ↵
Clifford Wolf
2014-06-15
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tests/realmath)
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Added tests/realmath to "make test"
Clifford Wolf
2014-06-15
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Improved AstNode::realAsConst for large numbers
Clifford Wolf
2014-06-15
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Improved realmath test bench
Clifford Wolf
2014-06-15
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Improved parsing of large integer constants
Clifford Wolf
2014-06-15
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Improved AstNode::asReal for large integers
Clifford Wolf
2014-06-15
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improved realmath test bench
Clifford Wolf
2014-06-14
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improved (fixed) conversion of real values to bit vectors
Clifford Wolf
2014-06-14
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progress in realmath test bench
Clifford Wolf
2014-06-14
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Fixed relational operators for const real expressions
Clifford Wolf
2014-06-14
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added first draft of real math testcase generator
Clifford Wolf
2014-06-14
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Progress in presentation
Clifford Wolf
2014-06-14
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Added %D and %c select commands
Clifford Wolf
2014-06-14
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Added support for math functions
Clifford Wolf
2014-06-14
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Added realexpr.v test case
Clifford Wolf
2014-06-14
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Added handling of real-valued parameters/localparams
Clifford Wolf
2014-06-14
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Implemented more real arithmetic
Clifford Wolf
2014-06-14
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Implemented basic real arithmetic
Clifford Wolf
2014-06-14
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Added real->int convertion in ast genrtlil
Clifford Wolf
2014-06-14
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Added Verilog lexer and parser support for real values
Clifford Wolf
2014-06-13
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Added read_verilog -sv options, added support for bit, logic,
Clifford Wolf
2014-06-12
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allways_ff, always_comb, and always_latch
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