Commit message (Expand)AuthorAge
* Added and (tests/tools/...)Clifford Wolf2014-02-19
* Merge branch 'master' of Wolf2014-02-18
| * Added "sat -dump_cnf"Clifford Wolf2014-02-18
| * Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
| * Improved non-verbose ezSAT::printDIMACS() formatClifford Wolf2014-02-18
| * Added "sat -initsteps"Clifford Wolf2014-02-18
* | Progress in presentationClifford Wolf2014-02-18
* | Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-18
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-17
* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-17
* Progress in presentationClifford Wolf2014-02-17
* Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-17
* Progress in presentationClifford Wolf2014-02-16
* Added some additional checks to techmapClifford Wolf2014-02-16
* Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-16
* Fixed handling of "keep" attribute on wires in opt_cleanClifford Wolf2014-02-16
* Added a warning note about error reporting to read_verilog help messageClifford Wolf2014-02-16
* Progress in presentationClifford Wolf2014-02-16
* Fixed use of selection in splitnets commandClifford Wolf2014-02-16
* Added recursion support to techmapClifford Wolf2014-02-16
* Progress in presentationClifford Wolf2014-02-16
* Progress in presentationClifford Wolf2014-02-16
* Improved support for constant functionsClifford Wolf2014-02-16
* Now we are in Yoys 0.2.0+ developmentClifford Wolf2014-02-16
* Tagging Yoys 0.2.0Clifford Wolf2014-02-16
* Added != support for relational select patternClifford Wolf2014-02-16
* Added iopadmap -bitsClifford Wolf2014-02-15
* Added ff and latch support to read_libertyClifford Wolf2014-02-15
* Bugfix in expression parser of read_libertyClifford Wolf2014-02-15
* Fixed dfflibmap for cell libraries with no set-reset-ffClifford Wolf2014-02-15
* Correctly convert constants to RTLIL (fixed undef handling)Clifford Wolf2014-02-15
* Added frontend (-f) option to autotest.shClifford Wolf2014-02-15
* Fixed opt_const handling of double invert with non-1 output widthClifford Wolf2014-02-15
* Added liberty frontendClifford Wolf2014-02-15
* Be more conservative with new const-function codeClifford Wolf2014-02-14
* Added support for FOR loops in function calls in parametersClifford Wolf2014-02-14
* Created basic support for function calls in parameter valuesClifford Wolf2014-02-14
* Added abc -keepff optionClifford Wolf2014-02-14
* updated default ABC command stringsClifford Wolf2014-02-13
* Updated ABCClifford Wolf2014-02-13
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Removed double blanks in ABC default command sequencesClifford Wolf2014-02-13
* Merge branch 'master' of Wolf2014-02-13
| * Merge pull request #26 from ahmedirfan1983/btorClifford Wolf2014-02-12
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| | * modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-12
| | * disabling splice command in the scriptAhmed Irfan2014-02-11
| | * register output correctedAhmed Irfan2014-02-11
| | * Merge branch 'master' of into btorAhmed Irfan2014-02-11
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| | * | added concat and slice cell translationAhmed Irfan2014-02-11