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* Improved make rules for profiling and debuggingClifford Wolf2013-11-22
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* Updated abcClifford Wolf2013-11-21
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* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-21
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* Fixed async proc detection in mem2regClifford Wolf2013-11-21
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
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* Fixed a bug in "add -global_input"Clifford Wolf2013-11-21
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* Added "proc_arst -global_arst" featureClifford Wolf2013-11-20
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* Fixed ilang parser: memory widthClifford Wolf2013-11-20
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* Added "add" command (only wires for now)Clifford Wolf2013-11-20
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* Another name resolution bugfix for generate blocksClifford Wolf2013-11-20
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* Implemented indexed part selectsClifford Wolf2013-11-20
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* Do not allow memory bit select on the left side of an assignmentClifford Wolf2013-11-20
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* Added "synthesis" in (synopsys|synthesis) comment supportClifford Wolf2013-11-20
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* Fixed name resolution of local tasks and functions in generate blockClifford Wolf2013-11-20
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* Implemented part/bit select on memory readClifford Wolf2013-11-20
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* Updated TODOs in README fileClifford Wolf2013-11-20
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* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-20
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* Added "make config-sudo"Clifford Wolf2013-11-19
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* Install simlib in datdirClifford Wolf2013-11-19
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* Large improvements in yosys-configClifford Wolf2013-11-19
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* Fixed parsing of module arguments when one type is used for many argsClifford Wolf2013-11-19
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* Renamed temp module generated by "abc" pass from "logic" to "netlist"Clifford Wolf2013-11-19
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* Added additional mem2reg testcaseClifford Wolf2013-11-18
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* Fixed two bugs in mem2reg functionality in AST frontendClifford Wolf2013-11-18
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* Added dumping of attributes in AST frontendClifford Wolf2013-11-18
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* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
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* Fixed mem2reg for reg usage outside always blockClifford Wolf2013-11-18
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* Added commented-out osu025 maping commands to cmos techmap exampleClifford Wolf2013-11-18
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* Added -v<level> option and some minor driver cleanupsClifford Wolf2013-11-17
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* Renamed ABCHGPULL to ABCPULL in MakefileClifford Wolf2013-11-16
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* Improved building of yosys-abcClifford Wolf2013-11-13
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* Fixed abc pass blif parser for constant bitsClifford Wolf2013-11-13
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* Fixed parsing of "parameter integer"Clifford Wolf2013-11-13
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* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
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* Added information on all internal cell types to internal checkerClifford Wolf2013-11-11
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* Call internal checker more oftenClifford Wolf2013-11-10
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* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09
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* Silenced a gcc warning in spice backendClifford Wolf2013-11-09
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* Added verification of SAT model to "eval -vloghammer_report" commandClifford Wolf2013-11-09
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* More undef-propagation related fixesClifford Wolf2013-11-08
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* Fixed handling of different signedness in power operandsClifford Wolf2013-11-08
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* Fixed keep attribute on wires in opt_cleanClifford Wolf2013-11-08
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* Implemented const folding of ternary op with undef selectClifford Wolf2013-11-08
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* Removed debug log from const_pow()Clifford Wolf2013-11-08
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* Fixed handling of power operatorClifford Wolf2013-11-07
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* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-07
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* Disabled const folding of ternary op when select is undefClifford Wolf2013-11-07
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* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
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* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-07
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* Fixed sign handling in constantsClifford Wolf2013-11-07
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