yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
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*	Various cleanups in Makefile, Renamed default configurations	Clifford Wolf	2014-07-31
*	Added compiler + compiler version + compiler flags to version string	Clifford Wolf	2014-07-31
*	Fixed build of verific bindings	Clifford Wolf	2014-07-31
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added "trace" command	Clifford Wolf	2014-07-31
*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31
*	Added "techmap -assert"	Clifford Wolf	2014-07-31
*	Reorganized stdcells.v (no actual code change, just moved and indented stuff)	Clifford Wolf	2014-07-31
*	Added "yosys -A"	Clifford Wolf	2014-07-31
*	Added "yosys -Q"	Clifford Wolf	2014-07-31
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30
*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30
*	Added write_file command	Clifford Wolf	2014-07-30
*	Added "make -j{N}" support to "make test"	Clifford Wolf	2014-07-30
*	Improvements in test_cell	Clifford Wolf	2014-07-30
*	New techmap default rules for $shr $sshr $shl $sshl	Clifford Wolf	2014-07-30
*	Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models	Clifford Wolf	2014-07-30
*	Added native support for shift operations to ezSAT	Clifford Wolf	2014-07-30
*	Added "log_dump_val_worker(char *v)"	Clifford Wolf	2014-07-30
*	Added CodingStyle document	Clifford Wolf	2014-07-30
*	Added "kernel/yosys.h" and "kernel/yosys.cc"	Clifford Wolf	2014-07-30
*	Added "test_cell" command	Clifford Wolf	2014-07-29
*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29
*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29
*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29
*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29
*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Removed left over debug code	Clifford Wolf	2014-07-28
*	Fixed part selects of parameters	Clifford Wolf	2014-07-28
*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28
*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28
*	Fixed width detection for part selects	Clifford Wolf	2014-07-28
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28
*	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28
*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28
*	Improvements in tests/vloghtb	Clifford Wolf	2014-07-28
*	Added techmap -extern	Clifford Wolf	2014-07-27
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
*	Added topological sorting to techmap	Clifford Wolf	2014-07-27
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27
*	Small improvements in PerformanceTimer API	Clifford Wolf	2014-07-27
*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27
*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27