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* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Added "techmap -share_map" optionClifford Wolf2013-11-24
* Early wire/reg/parameter width calculation in ast/simplifyClifford Wolf2013-11-24
* Updated TODOsClifford Wolf2013-11-24
* Fixed xilinx/example_sim_counter test benchClifford Wolf2013-11-24
* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-24
* Added support for signed parameters in ilangClifford Wolf2013-11-24
* Removed now obsolete test casesClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Added modelsim support to autotestClifford Wolf2013-11-24
* Fixed "flatten" top-module detection: Only use on fully selected designsClifford Wolf2013-11-24
* Fixed "make install" dependenciesClifford Wolf2013-11-24
* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-24
* Updated command-reference-manual.texClifford Wolf2013-11-23
* AppNote 010 typo fixes and correctionsClifford Wolf2013-11-23
* AppNote 010 progressClifford Wolf2013-11-23
* Improved handling of techmap special wiresClifford Wolf2013-11-23
* Improved handling of initialized registersClifford Wolf2013-11-23
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-23
* Making prograss on Appnote 010Clifford Wolf2013-11-23
* Progress on AppNote 010Clifford Wolf2013-11-22
* Started to write on AppNote 010: Verilog to BLIFClifford Wolf2013-11-22
* Updated command-reference-manual.texClifford Wolf2013-11-22
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Some driver changes/fixesClifford Wolf2013-11-22
* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-22
* Added more performance measurement infrastructureClifford Wolf2013-11-22
* Enable {* .. *} feature per default (removes dependency to REJECT feature in ...Clifford Wolf2013-11-22
* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-22
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Improved make rules for profiling and debuggingClifford Wolf2013-11-22
* Updated abcClifford Wolf2013-11-21
* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-21
* Fixed async proc detection in mem2regClifford Wolf2013-11-21
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Fixed a bug in "add -global_input"Clifford Wolf2013-11-21
* Added "proc_arst -global_arst" featureClifford Wolf2013-11-20
* Fixed ilang parser: memory widthClifford Wolf2013-11-20
* Added "add" command (only wires for now)Clifford Wolf2013-11-20
* Another name resolution bugfix for generate blocksClifford Wolf2013-11-20
* Implemented indexed part selectsClifford Wolf2013-11-20
* Do not allow memory bit select on the left side of an assignmentClifford Wolf2013-11-20
* Added "synthesis" in (synopsys|synthesis) comment supportClifford Wolf2013-11-20
* Fixed name resolution of local tasks and functions in generate blockClifford Wolf2013-11-20
* Implemented part/bit select on memory readClifford Wolf2013-11-20
* Updated TODOs in README fileClifford Wolf2013-11-20
* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-20
* Added "make config-sudo"Clifford Wolf2013-11-19
* Install simlib in datdirClifford Wolf2013-11-19