yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24
*	improvement in "stat"	Clifford Wolf	2015-10-24
*	Fixed driver conflict handling (various cmds)	Clifford Wolf	2015-10-24
*	equiv_purge bugfix, using SigChunk in Yosys namespace	Clifford Wolf	2015-10-24
*	Fixed handling of driver-driver conflicts in wreduce	Clifford Wolf	2015-10-24
*	Added equiv_mark command	Clifford Wolf	2015-10-23
*	Disabled "Skipping blackbox module" msg in show command	Clifford Wolf	2015-10-23
*	Added support for ":" as comment symbol after ;-parsing	Clifford Wolf	2015-10-23
*	Also merge $equiv cells in equiv_struct	Clifford Wolf	2015-10-23
*	Improvements in equiv_struct	Clifford Wolf	2015-10-23
*	Added equiv_purge	Clifford Wolf	2015-10-22
*	Added equiv_struct command	Clifford Wolf	2015-10-21
*	Improved inout handling in equiv_make	Clifford Wolf	2015-10-21
*	Progress on cell help messages	Clifford Wolf	2015-10-20
*	Progress on cell help messages	Clifford Wolf	2015-10-17
*	Progress in yosys-smtbmc	Clifford Wolf	2015-10-15
*	Fixed bug in verilog parser	Clifford Wolf	2015-10-15
*	Improvements in yosys-smtbmc	Clifford Wolf	2015-10-15
*	Bugfixes in handling of "keep" attribute on wires	Clifford Wolf	2015-10-15
*	More "yosys-smtbmc -c" fixes	Clifford Wolf	2015-10-14
*	Fixed yosys-smtbmc -c	Clifford Wolf	2015-10-14
*	Added "prep" command	Clifford Wolf	2015-10-14
*	Added more cell descriptions	Clifford Wolf	2015-10-14
*	Added first help messages for cell types	Clifford Wolf	2015-10-14
*	Added yosys-smtbmc copyright	Clifford Wolf	2015-10-14
*	Improvements in yosys-smtbmc	Clifford Wolf	2015-10-14
*	Added yosys-smtbmc	Clifford Wolf	2015-10-14
*	Implemented smtbmc.py -i	Clifford Wolf	2015-10-14
*	Added smtbmc.py	Clifford Wolf	2015-10-13
*	Added write_smt2 -wires	Clifford Wolf	2015-10-13
*	Added examples/ top-level directory	Clifford Wolf	2015-10-13
*	SystemVerilog also has assume(), added implicit -D FORMAL	Clifford Wolf	2015-10-13
*	Merge branch 'master' of https://github.com/rubund/yosys	Clifford Wolf	2015-10-13
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\| *	Use DESTDIR as defined in https://www.gnu.org/prep/standards/html_node/DESTDI...	Ruben Undheim	2015-10-11
\| *	Use LDFLAGS, CXXFLAGS and CPPFLAGS from the environment when building	Ruben Undheim	2015-10-11
* \|	Fixed "flatten" for unconnected inout ports	Clifford Wolf	2015-10-13
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*	Added support for "parameter" and "localparam" in global context	Clifford Wolf	2015-10-07
*	Fixed complexity of assigning to vectors in constant functions	Clifford Wolf	2015-10-01
*	Fixed detection of unconditional $readmem[hb]	Clifford Wolf	2015-09-30
*	Added edgetypes command	Clifford Wolf	2015-09-27
*	Some cleanups in qwp	Clifford Wolf	2015-09-26
*	Added "test_cell -noeval"	Clifford Wolf	2015-09-25
*	Added wreduce $mul support and fixed signed $mul opt_const bug	Clifford Wolf	2015-09-25
*	Bugfix in bram read-enable code	Clifford Wolf	2015-09-25
*	Bugfixes in $readmem[hb]	Clifford Wolf	2015-09-25
*	Bugfixes in writing of memories as Verilog	Clifford Wolf	2015-09-25
*	Fixed segfault in AstNode::asReal	Clifford Wolf	2015-09-25
*	Added read-enable to memory model	Clifford Wolf	2015-09-25
*	Added pivoting to qwp solver	Clifford Wolf	2015-09-24
*	Improved qwp performance	Clifford Wolf	2015-09-24