yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
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*	Added "stat -width"	Clifford Wolf	2014-08-22
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
*	Added DPI-C documentation to README file	Clifford Wolf	2014-08-22
*	Added support for non-standard <plugin>:<c_name> DPI syntax	Clifford Wolf	2014-08-22
*	Archibald Rust and Clifford Wolf: ffi-based dpi_call()	Clifford Wolf	2014-08-22
*	Added "plugin" command	Clifford Wolf	2014-08-22
*	Updated ABC to 4d547a5e065b	Clifford Wolf	2014-08-22
*	Cosmetic changes to FSM tests	Clifford Wolf	2014-08-21
*	Fixed small memory leak in ast simplify	Clifford Wolf	2014-08-21
*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21
*	Fixed memory leak in DPI function calls	Clifford Wolf	2014-08-21
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-08-21
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\| *	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19
* \|	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
* \|	Added support for global tasks and functions	Clifford Wolf	2014-08-21
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*	Using "via_celltype" in $mul carry-save-acc implementation	Clifford Wolf	2014-08-18
*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18
*	Performance fix for new $__lcu techmap rule	Clifford Wolf	2014-08-18
*	Replaced recursive lcu scheme with bk adder	Clifford Wolf	2014-08-18
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18
*	Fixed proc_{self,share}_dirname error handling	Clifford Wolf	2014-08-17
*	Makefile fixes	Clifford Wolf	2014-08-17
*	Improved AST ProcessGenerator performance	Clifford Wolf	2014-08-17
*	Improved sig.remove2() performance	Clifford Wolf	2014-08-17
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17
*	Added stackmap<> container	Clifford Wolf	2014-08-17
*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17
*	Added module->uniquify()	Clifford Wolf	2014-08-16
*	Fixed AOI/OAI expr handling in verilog backend	Clifford Wolf	2014-08-16
*	Multiply using a carry-save accumulator	Clifford Wolf	2014-08-16
*	Added "test_cell -s <seed>"	Clifford Wolf	2014-08-16
*	AST ProcessGenerator: replaced subst__{from,to} with subst__map	Clifford Wolf	2014-08-16
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16
*	Added CellTypes::cell_evaluable()	Clifford Wolf	2014-08-16
*	Changes in techmap $__alu interface	Clifford Wolf	2014-08-16
*	Added "opt -fast"	Clifford Wolf	2014-08-16
*	Added log_spacer()	Clifford Wolf	2014-08-16
*	Bugfix in iopadmap	Clifford Wolf	2014-08-15
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	Removed old doc references to $safe_pmux	Clifford Wolf	2014-08-15
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
*	Added Frontend "+/" filename syntax for files from proc_share_dir	Clifford Wolf	2014-08-15
*	document "techmap -map %<design-name>"	Clifford Wolf	2014-08-15
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14
*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14