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* Using $pos models for $bu0Clifford Wolf2014-09-03
* Fixed "test_cells -vlog"Clifford Wolf2014-09-03
* Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-03
* Undef-related fixes in simlib $alu modelClifford Wolf2014-09-02
* Improvements in "test_cell -vlog"Clifford Wolf2014-09-02
* Added test_cell -vlogClifford Wolf2014-09-02
* Create a default selection stack in RTLIL::Design::Design()Clifford Wolf2014-09-02
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-02
* Added SAT testing to test_cell eval stageClifford Wolf2014-09-02
* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-02
* Removed yosys-svgviewerClifford Wolf2014-09-02
* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-02
* Added $alu support to test_cellClifford Wolf2014-09-01
* Added ConstEval model for $alu cellsClifford Wolf2014-09-01
* Added SAT model for $alu cellsClifford Wolf2014-09-01
* Fixed "test_cell -simlib all"Clifford Wolf2014-09-01
* Added "test_cell -simlib -v"Clifford Wolf2014-09-01
* Added "techmap -autoproc"Clifford Wolf2014-09-01
* Fixes in old SAT example.ysClifford Wolf2014-09-01
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-01
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
* Added eval testing to test_cellClifford Wolf2014-08-31
* Fixed return size of const_*() eval functionsClifford Wolf2014-08-31
* Added RTLIL::Const::size()Clifford Wolf2014-08-31
* Added eval model for $lut cellsClifford Wolf2014-08-31
* Typo fixes in cell->*Param() APIClifford Wolf2014-08-31
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
* Added design->scratchpadClifford Wolf2014-08-30
* Added $alu cell typeClifford Wolf2014-08-30
* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-30
* Improved write address decoder generation memory_mapClifford Wolf2014-08-30
* Fixed module->addPmux()Clifford Wolf2014-08-30
* Using worker class in memory_mapClifford Wolf2014-08-30
* Replaced $__alu CO/CS outputs with full-width CO outputClifford Wolf2014-08-30
* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-30
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-30
* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-30
* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-27
* Fixed printing of multi-line Makefile.confClifford Wolf2014-08-27
* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-26
* Print Makefile.conf as make info messageClifford Wolf2014-08-26
* Checking for valid CONFIG value in MakefileClifford Wolf2014-08-25
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-24
* Added some additional log messages to opt_constClifford Wolf2014-08-24
* Added is_signed argument to SigSpec.as_int() and Const.as_int()Clifford Wolf2014-08-24
* azonenberg: Make dump_vcd save model when temporal induction fails due to ste...Clifford Wolf2014-08-24
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-23
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23