yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16
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*	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	Clifford Wolf	2014-06-16
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*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16
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*	Added more calls to "hierarchy" to README file	Clifford Wolf	2014-06-15
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*	Removed long running tests from tests/simple/realexpr.v (replaced by ↵	Clifford Wolf	2014-06-15
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*	Added tests/realmath to "make test"	Clifford Wolf	2014-06-15
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*	Improved AstNode::realAsConst for large numbers	Clifford Wolf	2014-06-15
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*	Improved realmath test bench	Clifford Wolf	2014-06-15
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*	Improved parsing of large integer constants	Clifford Wolf	2014-06-15
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*	Improved AstNode::asReal for large integers	Clifford Wolf	2014-06-15
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*	improved realmath test bench	Clifford Wolf	2014-06-14
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*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14
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*	progress in realmath test bench	Clifford Wolf	2014-06-14
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*	Fixed relational operators for const real expressions	Clifford Wolf	2014-06-14
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*	added first draft of real math testcase generator	Clifford Wolf	2014-06-14
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*	Progress in presentation	Clifford Wolf	2014-06-14
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*	Added %D and %c select commands	Clifford Wolf	2014-06-14
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*	Added support for math functions	Clifford Wolf	2014-06-14
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*	Added realexpr.v test case	Clifford Wolf	2014-06-14
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*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14
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*	Implemented more real arithmetic	Clifford Wolf	2014-06-14
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*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14
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*	Added real->int convertion in ast genrtlil	Clifford Wolf	2014-06-14
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*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
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*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12
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*	Now we are in Yoys 0.3.0+ development	Clifford Wolf	2014-06-08
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*	Tagging Yosys 0.3.0	Clifford Wolf	2014-06-08
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*	Updated ABC to 7600ffb9340c	Clifford Wolf	2014-06-08
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*	added tests for new verilog features	Clifford Wolf	2014-06-07
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*	fixed cell array handling of positional arguments	Clifford Wolf	2014-06-07
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*	Add support for cell arrays	Clifford Wolf	2014-06-07
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*	Added support for repeat stmt in const functions	Clifford Wolf	2014-06-07
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*	further improved const function support	Clifford Wolf	2014-06-07
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*	made the generate..endgenrate keywords optional	Clifford Wolf	2014-06-06
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*	improved const function support	Clifford Wolf	2014-06-06
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*	fix functions with no block (but single statement, loop, etc.)	Clifford Wolf	2014-06-06
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*	Added tests/simple/repwhile.v	Clifford Wolf	2014-06-06
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*	improved ast simplify of const functions	Clifford Wolf	2014-06-06
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*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
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*	Improved error message for options after front-end filename arguments	Clifford Wolf	2014-06-04
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*	added tee cmd	Clifford Wolf	2014-06-03
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*	Fixed log messages in memory_dff	Clifford Wolf	2014-06-01
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*	Updated ABC to rev fa4404b395f0	Clifford Wolf	2014-05-29
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*	Merge pull request #36 from hansiglaser/master	Clifford Wolf	2014-05-29
\|\ \| \| \| \|	Various changes merged
\| *	added log_header to miter and expose pass, show cell type for exposed ports	Johann Glaser	2014-05-28
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\| *	new flags -ignore_miss_func and -ignore_miss_dir for read_liberty	Johann Glaser	2014-05-28
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\| *	be more verbose when techmap yielded processes	Johann Glaser	2014-05-26
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*	Fixed bug in opt_reduce (see vloghammer issue_044)	Clifford Wolf	2014-05-12
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*	fixed syntax error in dot file created by "show" command	Clifford Wolf	2014-05-10
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-05-09
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