yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Removed debug code from write_smt2	Clifford Wolf	2015-06-14
*	Modernized memory_dff (and fixed a bug)	Clifford Wolf	2015-06-14
*	Added "memory -nordff"	Clifford Wolf	2015-06-14
*	Added write_smt2 -mem	Clifford Wolf	2015-06-14
*	Makefile fix for YosysJS build	Clifford Wolf	2015-06-11
*	Fixed cstr_buf for std::string with small string optimization	Clifford Wolf	2015-06-11
*	Improvements in cellaigs.cc and "json -aig"	Clifford Wolf	2015-06-11
*	AigMaker refactoring	Clifford Wolf	2015-06-10
*	Added "json -aig"	Clifford Wolf	2015-06-10
*	Renamed "aig" to "aigmap"	Clifford Wolf	2015-06-10
*	Fixed cellaigs port extending	Clifford Wolf	2015-06-10
*	Added "aig" pass	Clifford Wolf	2015-06-09
*	synth_ice40 now flattens by default	Clifford Wolf	2015-06-09
*	Added cellaigs API	Clifford Wolf	2015-06-09
*	Merge clock inverters in memory_dff	Clifford Wolf	2015-06-09
*	Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys	Clifford Wolf	2015-06-09
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\| *	$mem cell in verilog backend : grouped writes by clock	luke whittlesey	2015-06-08
\| *	Bug fix in $mem verilog backend + changed tests/bram flow of make test.	luke whittlesey	2015-06-04
* \|	Fixed "avail_parameters" handling in module clone/copy	Clifford Wolf	2015-06-08
* \|	Added log_dump() support for IdStrings	Clifford Wolf	2015-06-08
* \|	Fixed handling of parameters with reversed range	Clifford Wolf	2015-06-08
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*	Added opt_share -share_all	Clifford Wolf	2015-05-31
*	Added iCE40 PLL cells	Clifford Wolf	2015-05-31
*	Added liberty dont_use support to dfflibmap	Clifford Wolf	2015-05-31
*	Fixed signedness of genvar expressions	Clifford Wolf	2015-05-29
*	Added output args to synth_ice40	Clifford Wolf	2015-05-26
*	Improvements in BLIF front-end	Clifford Wolf	2015-05-24
*	improved ice40 SB_IO sim model	Clifford Wolf	2015-05-23
*	Improved "flatten" handlings of inout ports	Clifford Wolf	2015-05-23
*	Added simple $dlatch support to opt_rmdff	Clifford Wolf	2015-05-23
*	Added ice40 SB_IO sim model	Clifford Wolf	2015-05-23
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2015-05-22
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\| *	Some fixes for $mem in verilog back-end	Clifford Wolf	2015-05-20
* \|	preserve used $-wires with init attribute in opt_clean	Clifford Wolf	2015-05-22
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*	bugfix in blif front-end	Clifford Wolf	2015-05-18
*	added vloghtb test_febe.sh	Clifford Wolf	2015-05-17
*	Improved .latch support in BLIF front-end	Clifford Wolf	2015-05-17
*	Added read_blif command	Clifford Wolf	2015-05-17
*	Generalized blifparse API	Clifford Wolf	2015-05-17
*	abc/blifparse files reorganization	Clifford Wolf	2015-05-17
*	Verific build fixes	Clifford Wolf	2015-05-17
*	Added .barbuf support to abc BLIF parser	Clifford Wolf	2015-05-13
*	changed file() to open() in python scripts	Clifford Wolf	2015-05-11
*	Merge pull request #63 from wluker/verilog-backend-mem	Clifford Wolf	2015-05-11
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\| *	Fixed bug in $mem cell verilog code generation.	luke whittlesey	2015-05-11
* \|	Disabled broken $mem support in verilog backend	Clifford Wolf	2015-05-10
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*	Merge pull request #62 from wluker/verilog-backend-mem	Clifford Wolf	2015-05-10
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\| *	Made changes recommended by Clifford Wolf ...	luke whittlesey	2015-05-10
\| *	Verilog backend for $mem cells should now be able to handle different	luke whittlesey	2015-05-08
\| *	Added support for $mem cells in the verilog backend.	luke whittlesey	2015-05-07
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