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* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
* Added DPI-C documentation to README fileClifford Wolf2014-08-22
* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-22
* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-22
* Added "plugin" commandClifford Wolf2014-08-22
* Updated ABC to 4d547a5e065bClifford Wolf2014-08-22
* Cosmetic changes to FSM testsClifford Wolf2014-08-21
* Fixed small memory leak in ast simplifyClifford Wolf2014-08-21
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-21
* Added AstNode::asInt()Clifford Wolf2014-08-21
* Fixed memory leak in DPI function callsClifford Wolf2014-08-21
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-08-21
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| * Added mod->addGate() methods for new gate typesClifford Wolf2014-08-19
* | Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
* | Added support for global tasks and functionsClifford Wolf2014-08-21
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* Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-18
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-18
* Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-18
* Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-18
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-18
* Fixed proc_{self,share}_dirname error handlingClifford Wolf2014-08-17
* Makefile fixesClifford Wolf2014-08-17
* Improved AST ProcessGenerator performanceClifford Wolf2014-08-17
* Improved sig.remove2() performanceClifford Wolf2014-08-17
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-17
* Added stackmap<> containerClifford Wolf2014-08-17
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Added module->uniquify()Clifford Wolf2014-08-16
* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-16
* Multiply using a carry-save accumulatorClifford Wolf2014-08-16
* Added "test_cell -s <seed>"Clifford Wolf2014-08-16
* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Added CellTypes::cell_evaluable()Clifford Wolf2014-08-16
* Changes in techmap $__alu interfaceClifford Wolf2014-08-16
* Added "opt -fast"Clifford Wolf2014-08-16
* Added log_spacer()Clifford Wolf2014-08-16
* Bugfix in iopadmapClifford Wolf2014-08-15
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Removed old doc references to $safe_pmuxClifford Wolf2014-08-15
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* Added Frontend "+/" filename syntax for files from proc_share_dirClifford Wolf2014-08-15
* document "techmap -map %<design-name>"Clifford Wolf2014-08-15
* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-15
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
* Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-14
* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-14
* Fixed handling of task outputsClifford Wolf2014-08-14