Commit message (Expand)AuthorAge
* Keep viewport transform stable on reload in yosys-svgviewerClifford Wolf2013-03-27
* Added check: only one module for "show" unless format is "ps"Clifford Wolf2013-03-27
* Now using SVG and yosys-svgviewer per default in show commandClifford Wolf2013-03-27
* Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlibClifford Wolf2013-03-27
* Imported svgviewer from qt4.8Clifford Wolf2013-03-27
* Create nice errors when calling RTLIL::Module::derive() of base classClifford Wolf2013-03-26
* Collect parameters in hierarchy -generate (and do nothing with them)Clifford Wolf2013-03-26
* Tiny bugfix in simlib.vClifford Wolf2013-03-26
* Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-26
* Fixed handling of unconditional generate blocksClifford Wolf2013-03-26
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
* Improved verbose output of subcircuitClifford Wolf2013-03-25
* Improved method for finding fsm_expand candidatesClifford Wolf2013-03-25
* Added hierarchy -generate command for generating skeletton modulesClifford Wolf2013-03-25
* Changed fsm_expand to merge multiplexers more aggressivelyClifford Wolf2013-03-24
* Renamed hansimem.v test case to mem_arst.vClifford Wolf2013-03-24
* Fixed handling of show -viewerClifford Wolf2013-03-24
* Fixed handling of internal signals in show commandClifford Wolf2013-03-24
* Improved show -colors color assignmentsClifford Wolf2013-03-24
* Added show -strech and renamed -widthlabels to -widthClifford Wolf2013-03-24
* Added -widthlabels options to chow commandClifford Wolf2013-03-24
* Added -notypes option to intersynth backendClifford Wolf2013-03-24
* Reorganized TODOsClifford Wolf2013-03-24
* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
* Fixed stdcells.v for $adff with undef reset valueClifford Wolf2013-03-24
* Another fix in mem2reg ast simplify logicClifford Wolf2013-03-24
* Added -colors option to show commandClifford Wolf2013-03-24
* Added hansimem testcase (memory with async reset)Clifford Wolf2013-03-24
* Improved mem2reg handling in ast simplifierClifford Wolf2013-03-24
* Fixed gcc build (intersynth backend)Clifford Wolf2013-03-23
* Tiny fixes to verilog parserClifford Wolf2013-03-23
* Various improvements in intersynth backendClifford Wolf2013-03-23
* Added intersynth backendClifford Wolf2013-03-23
* Added help -write-tex-command-reference-manual optionClifford Wolf2013-03-21
* Added eclipse CDT project files to .gitignoreClifford Wolf2013-03-21
* Added -S option for simple synthesis to gate logicClifford Wolf2013-03-21
* Avoid verilog-2k in verilog backendClifford Wolf2013-03-21
* Disabled the per-default dumping of ILANG codeClifford Wolf2013-03-21
* Added -nomap option to memory passClifford Wolf2013-03-21
* Merge branch 'hansiglaser-master'Clifford Wolf2013-03-19
| * added optimizations for single-bit $eq/$ne with constant input to opt_constClifford Wolf2013-03-19
| * improved $mux optimization in opt_constClifford Wolf2013-03-19
| * keep $mux and $_MUX_ optimizations separate in opt_constClifford Wolf2013-03-19
| * added a TODOJohann Glaser2013-03-18
| * added one more suggestion to optimize MUXes in pass "opt_const"Johann Glaser2013-03-18
| * also optimize single-bit "$mux" cells in pass "opt_const", added suggestionsJohann Glaser2013-03-18
| * fixed a crash when lines start with whitespaceJohann Glaser2013-03-18
| * added description of Makefile include files for build configurationJohann Glaser2013-03-18
* More TODOs in READMEClifford Wolf2013-03-18
* Merge branch 'hansi'Clifford Wolf2013-03-18