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* Fixed subcircuit allowOverlap=false corner caseClifford Wolf2013-03-03
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* Added support for #x:<num> select stmtClifford Wolf2013-03-03
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* Handle known inout ports as outputs in show commandClifford Wolf2013-03-03
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* Fixed memory corruption in subcircuit minerClifford Wolf2013-03-03
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* Minor hotfixes (mostly gcc build fixes)Clifford Wolf2013-03-03
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* Added library support to celltypes class and show passClifford Wolf2013-03-03
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* Implemented general handler for selection argumentsClifford Wolf2013-03-03
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* Finished "extract -mine" featureClifford Wolf2013-03-02
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* More fun with subcircuit miningClifford Wolf2013-03-02
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* Added -mine option to extract pass (not finished)Clifford Wolf2013-03-02
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* subcircuit library: implied allExtern for miningClifford Wolf2013-03-02
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* Added frequent subcircuit miner to subcircuit libraryClifford Wolf2013-03-02
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* Added help messages for fsm_* passesClifford Wolf2013-03-01
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* Added help messages to memory_* passesClifford Wolf2013-03-01
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* Added help messages to proc_* passesClifford Wolf2013-03-01
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* Added help messages for opt_* passesClifford Wolf2013-03-01
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* Added id2cstr APIClifford Wolf2013-03-01
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* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-01
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* Do not unescape identifiers starting with \$Clifford Wolf2013-03-01
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* Fixed "make qtcreator" (we now have a libs/ directory)Clifford Wolf2013-03-01
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* Added more help messagesClifford Wolf2013-03-01
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* Improved help message for "shell" commandClifford Wolf2013-02-28
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* Added help command to README (and some other README changes)Clifford Wolf2013-02-28
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* Added online help for "show" and "hierarchy" commandsClifford Wolf2013-02-28
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* Added help for command line optionsClifford Wolf2013-02-28
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* Added help msg to select command (and minor improvements)Clifford Wolf2013-02-28
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* Added more help messages (extract, abc, dfflibmap)Clifford Wolf2013-02-28
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* Added "help" commandClifford Wolf2013-02-28
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* Added port swapping and compatible types to "extract" passClifford Wolf2013-02-28
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* Added "extract -constports" featureClifford Wolf2013-02-27
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* Changed default frontend for "-" to "script" (was: "ilang")Clifford Wolf2013-02-27
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* Fixed "extract" pass for non-optimized needlesClifford Wolf2013-02-27
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* Added support for simple gates with one constant input to opt_constClifford Wolf2013-02-27
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* Added extract -verbose and -map ilang supportClifford Wolf2013-02-27
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* Implemented basic functionality of "extract" passClifford Wolf2013-02-27
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* Added support for constant signals in "extract" passClifford Wolf2013-02-27
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* Added "extract" pass (not functional yet)Clifford Wolf2013-02-27
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* Added some additional TODO itemsClifford Wolf2013-02-27
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* Fixed typo in READMEClifford Wolf2013-02-27
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* Added copyright statement to readme fileClifford Wolf2013-02-27
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* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
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* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
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* Merge pull request #2 from mschmoelzer/masterClifford Wolf2013-02-24
|\ | | | | "fsm_export" pass: fix KISS file generation.
| * "fsm_export" pass: fix KISS file generation.Martin Schmölzer2013-02-23
|/ | | | | | | | | | | The KISS file format now follows the conventions specified in "Logic Synthesis and Optimization Benchmarks User Guide", Version 3.0 by Saeyang Yang. This change ensures interoperability with the "trfsmgen" program by Johann Glaser. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
* Added support for "always @(*)"Clifford Wolf2013-01-16
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* Merge pull request #1 from mschmoelzer/masterClifford Wolf2013-01-08
|\ | | | | Add support for "fsm_export" synthesis attributes to fsm_export pass
| * Merge remote-tracking branch 'upstream/master'Martin Schmölzer2013-01-08
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* | Added "getting started" section to READMEClifford Wolf2013-01-06
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* | Improvements in command shellClifford Wolf2013-01-06
| | | | | | | | | | | | - Added 'shell' command (run interactive shell from synth script) - Added support for ; as cmd seperator as in "proc; opt" - Fixed c++ static initialization order problem with pass register
| * Add support for "fsm_export" synthesis attributes to fsm_export pass.Martin Schmölzer2013-01-08
|/ | | | | | | | | | | | | | This allows to specify the file name for exported files directly in the HDL source via the fsm_export=... attribute on the FSM state register. Verilog example: (* fsm_export="my_fsm.kiss2" *) reg [3:0] state; The fsm_export pass now also accepts the option "-noauto". This causes only FSMs with the fsm_export attribute to be exported, any other FSMs are ignored. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>