yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added "abc -D" for setting delay target	Clifford Wolf	2014-08-14
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*	Updated ABC to 4935c2b946de	Clifford Wolf	2014-08-14
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*	Added techmap support for actual lookahead carry unit	Clifford Wolf	2014-08-13
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*	Preparations for lookahead ALU support in techmap.v	Clifford Wolf	2014-08-13
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*	Filter ANSI escape sequences from ABC output	Clifford Wolf	2014-08-13
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*	New interface for $__alu in techmap.v	Clifford Wolf	2014-08-13
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*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13
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*	Fixed handling of constant-true branches in proc_clean	Clifford Wolf	2014-08-12
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*	Added test_verific mode to tests/fsm/generate.py	Clifford Wolf	2014-08-12
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*	Fixed SigBit(RTLIL::Wire *wire) constructor	Clifford Wolf	2014-08-12
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*	Fixed building verific bindings	Clifford Wolf	2014-08-12
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*	Added multi-dim memory test (requires iverilog git head)	Clifford Wolf	2014-08-12
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*	Another build fix by americanrouter (via reddit)	Clifford Wolf	2014-08-11
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*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10
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*	Fixed "share" for complex scenarios with never-active cells	Clifford Wolf	2014-08-09
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*	Do not share any $reduce_* cells (its complicated and not worth it anyways)	Clifford Wolf	2014-08-09
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*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09
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*	Improved FSM tests	Clifford Wolf	2014-08-08
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*	Another fsm_extract bugfix	Clifford Wolf	2014-08-08
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*	Fixed "fsm -export"	Clifford Wolf	2014-08-08
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*	Fixed sharing of reduce operator	Clifford Wolf	2014-08-08
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*	Fixed fsm_extract for wreduced muxes	Clifford Wolf	2014-08-08
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*	Added FSM test bench	Clifford Wolf	2014-08-08
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*	Added "sat -prove-skip"	Clifford Wolf	2014-08-08
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*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07
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*	Use "-keepdc" in "miter -equiv -flatten"	Clifford Wolf	2014-08-07
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*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07
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*	Added adff2dff.v (for techmap -share_map)	Clifford Wolf	2014-08-07
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*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
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*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06
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*	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05
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*	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05
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*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05
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*	Added mux support to wreduce command	Clifford Wolf	2014-08-05
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*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
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*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05
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*	Added "show -signed"	Clifford Wolf	2014-08-04
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*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04
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*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03
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*	Added "wreduce" to some of the standard test benches	Clifford Wolf	2014-08-03
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*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03
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*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03
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*	Added query() API to ModIndex	Clifford Wolf	2014-08-03
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*	Added ID() macro for static IdStrings	Clifford Wolf	2014-08-03
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*	Implemented recursive techmap	Clifford Wolf	2014-08-03
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*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03
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*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02
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*	Fixed a va_list corruption in logv_error()	Clifford Wolf	2014-08-02
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