yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
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* \|	Added selection support for r: and selection with relational operators	Clifford Wolf	2014-02-05
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*	presentation progress	Clifford Wolf	2014-02-05
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*	presentation progress	Clifford Wolf	2014-02-05
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*	Added read_verilog -setattr	Clifford Wolf	2014-02-05
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*	Added setattr and setparam commands	Clifford Wolf	2014-02-05
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*	Updated todo items in README file	Clifford Wolf	2014-02-05
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*	Removed old unused files from tests/	Clifford Wolf	2014-02-05
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*	Added support for dump -append	Clifford Wolf	2014-02-04
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*	Throw errors if non-existing selection variables are used	Clifford Wolf	2014-02-04
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*	Added select -none	Clifford Wolf	2014-02-04
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*	presentation progress	Clifford Wolf	2014-02-04
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*	Fixed detection of init attribute in opt_rmdff	Clifford Wolf	2014-02-04
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*	Added support for inline commands to abc -script	Clifford Wolf	2014-02-04
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*	presentation progress	Clifford Wolf	2014-02-04
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*	Added hierarchy -purge_lib option	Clifford Wolf	2014-02-04
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*	Added test cases for sat command	Clifford Wolf	2014-02-04
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*	added sat -falsify	Clifford Wolf	2014-02-04
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*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04
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*	Improved handling of reg init in opt_share and opt_rmdff	Clifford Wolf	2014-02-04
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*	presentation progress	Clifford Wolf	2014-02-04
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*	presentation progress	Clifford Wolf	2014-02-03
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*	Addred sat option -ignore_unknown_cells	Clifford Wolf	2014-02-03
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
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*	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	Clifford Wolf	2014-02-03
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*	More opt_const -mux_bool features	Clifford Wolf	2014-02-02
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*	presentation progress	Clifford Wolf	2014-02-02
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*	Added opt_const -mux_bool	Clifford Wolf	2014-02-02
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*	Added support for inverter chains to opt_const	Clifford Wolf	2014-02-02
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*	Added RTLIL::SigSpec::to_single_sigbit()	Clifford Wolf	2014-02-02
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*	Only generate write-enable $and if WE is not constant 1 in memory_map	Clifford Wolf	2014-02-02
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*	Added constant-clock case to opt_rmdff	Clifford Wolf	2014-02-02
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*	presentation progress	Clifford Wolf	2014-02-02
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*	Added show -notitle option	Clifford Wolf	2014-02-02
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*	Added delete command	Clifford Wolf	2014-02-02
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*	Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax	Clifford Wolf	2014-02-02
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*	presentation progress	Clifford Wolf	2014-02-02
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*	presentation progress	Clifford Wolf	2014-02-02
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*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02
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*	Fixed a bug in miter command	Clifford Wolf	2014-02-01
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*	Added sat -show-inputs and -show-outputs	Clifford Wolf	2014-02-01
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*	Added show -color support for cells and finished show -label implementation	Clifford Wolf	2014-02-01
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*	Fixed comment/eol parsing in ilang frontend	Clifford Wolf	2014-02-01
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
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*	Added note about SystemVerilog assert statement to README	Clifford Wolf	2014-02-01
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*	Added miter command	Clifford Wolf	2014-02-01
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*	Progress on presentation	Clifford Wolf	2014-01-31
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*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31
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*	presentation progress	Clifford Wolf	2014-01-30
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*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30
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*	Added yosys -H for command list	Clifford Wolf	2014-01-30
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