yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Strictly zero-extend unsigned A-inputs of shift operations	Clifford Wolf	2014-03-06
*	Switched to EZMINISAT_SIMPSOLVER as default SAT solver	Clifford Wolf	2014-03-05
*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05
*	Fixed merging of compatible wire decls in AST frontend	Clifford Wolf	2014-03-05
*	Bugfix in recursive AST simplification	Clifford Wolf	2014-03-05
*	fixed freduce for Minisat::SimpSolver: use frozen_literal()	Clifford Wolf	2014-03-03
*	ezSAT: Added frozen_literal() API	Clifford Wolf	2014-03-03
*	ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressions	Clifford Wolf	2014-03-03
*	Added ezSAT::eliminated API to help the SAT solver remember eliminated variables	Clifford Wolf	2014-03-01
*	ezSAT bugfix: don't call virtual methods in base class constructor	Clifford Wolf	2014-03-01
*	Removed ezSAT::assumed() API	Clifford Wolf	2014-03-01
*	Removed ezSAT built-in brute-froce solver	Clifford Wolf	2014-03-01
*	Fixed vhdl2verilog temp dir name	Clifford Wolf	2014-03-01
*	Fixed vhdl2verilog help message	Clifford Wolf	2014-03-01
*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27
*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26
*	Added support for $bu0 to SatGen	Clifford Wolf	2014-02-26
*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24
*	Added support for Minisat::SimpSolver + ezSAT frezze() API	Clifford Wolf	2014-02-23
*	Fixed small memory leak in Pass::call()	Clifford Wolf	2014-02-23
*	Fixed bug in generation of undefs for $memwr MUXes	Clifford Wolf	2014-02-22
*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22
*	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22
*	Added ezMiniSat EZMINISAT_INCREMENTAL compile-time option	Clifford Wolf	2014-02-22
*	Made MiniSat solver backend configurable in ezminisat.h	Clifford Wolf	2014-02-22
*	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	Clifford Wolf	2014-02-21
*	Added vhdl2verilog	Clifford Wolf	2014-02-21
*	Progress in presentation	Clifford Wolf	2014-02-21
*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21
*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21
*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21
*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21
*	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	Clifford Wolf	2014-02-21
*	Progress in presentation	Clifford Wolf	2014-02-21
*	Progress in presentation	Clifford Wolf	2014-02-20
*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20
*	Added "extract -ignore_parameters" and "extract -ignore_param ..."	Clifford Wolf	2014-02-20
*	Added "extract -map %<design_name>"	Clifford Wolf	2014-02-20
*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20
*	Progress in presentation	Clifford Wolf	2014-02-20
*	Added connwrappers command	Clifford Wolf	2014-02-20
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20
*	Progress in presentation	Clifford Wolf	2014-02-20
*	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	Clifford Wolf	2014-02-19
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-18
\|\
\| *	Added "sat -dump_cnf"	Clifford Wolf	2014-02-18
\| *	Coding style corrections in SatHelper::dump_model_to_vcd()	Clifford Wolf	2014-02-18
\| *	Improved non-verbose ezSAT::printDIMACS() format	Clifford Wolf	2014-02-18
\| *	Added "sat -initsteps"	Clifford Wolf	2014-02-18
* \|	Progress in presentation	Clifford Wolf	2014-02-18