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* Strictly zero-extend unsigned A-inputs of shift operationsClifford Wolf2014-03-06
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* Switched to EZMINISAT_SIMPSOLVER as default SAT solverClifford Wolf2014-03-05
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* Include id2ast pointers when dumping ASTClifford Wolf2014-03-05
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* Fixed merging of compatible wire decls in AST frontendClifford Wolf2014-03-05
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* Bugfix in recursive AST simplificationClifford Wolf2014-03-05
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* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-03
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* ezSAT: Added frozen_literal() APIClifford Wolf2014-03-03
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* ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressionsClifford Wolf2014-03-03
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* Added ezSAT::eliminated API to help the SAT solver remember eliminated variablesClifford Wolf2014-03-01
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* ezSAT bugfix: don't call virtual methods in base class constructorClifford Wolf2014-03-01
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* Removed ezSAT::assumed() APIClifford Wolf2014-03-01
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* Removed ezSAT built-in brute-froce solverClifford Wolf2014-03-01
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* Fixed vhdl2verilog temp dir nameClifford Wolf2014-03-01
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* Fixed vhdl2verilog help messageClifford Wolf2014-03-01
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* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
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* Fixed bit-extending in $mux argument (use $bu0 instead of $pos)Clifford Wolf2014-02-26
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* Added support for $bu0 to SatGenClifford Wolf2014-02-26
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* Don't blow up constants unneccessarily in Verilog frontendClifford Wolf2014-02-24
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* Added support for Minisat::SimpSolver + ezSAT frezze() APIClifford Wolf2014-02-23
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* Fixed small memory leak in Pass::call()Clifford Wolf2014-02-23
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* Fixed bug in generation of undefs for $memwr MUXesClifford Wolf2014-02-22
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* Fixed bug (typo) in passes/opt/opt_const.ccClifford Wolf2014-02-22
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* Added $lut support to blif backend (by user eddiehung from reddit)Clifford Wolf2014-02-22
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* Added ezMiniSat EZMINISAT_INCREMENTAL compile-time optionClifford Wolf2014-02-22
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* Made MiniSat solver backend configurable in ezminisat.hClifford Wolf2014-02-22
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* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
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* Added vhdl2verilogClifford Wolf2014-02-21
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* Progress in presentationClifford Wolf2014-02-21
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* Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-21
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* Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-21
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* Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-21
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* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-21
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* Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-21
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* Progress in presentationClifford Wolf2014-02-21
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* Progress in presentationClifford Wolf2014-02-20
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* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-20
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* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-20
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* Added "extract -map %<design_name>"Clifford Wolf2014-02-20
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* Added "design -push" and "design -pop"Clifford Wolf2014-02-20
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* Progress in presentationClifford Wolf2014-02-20
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* Added connwrappers commandClifford Wolf2014-02-20
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* Cleanups in handling of read_verilog -defer and -icellsClifford Wolf2014-02-20
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* Progress in presentationClifford Wolf2014-02-20
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* Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-19
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-18
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| * Added "sat -dump_cnf"Clifford Wolf2014-02-18
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| * Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
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| * Improved non-verbose ezSAT::printDIMACS() formatClifford Wolf2014-02-18
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| * Added "sat -initsteps"Clifford Wolf2014-02-18
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* | Progress in presentationClifford Wolf2014-02-18
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