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* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-22
* Added more performance measurement infrastructureClifford Wolf2013-11-22
* Enable {* .. *} feature per default (removes dependency to REJECT feature in ...Clifford Wolf2013-11-22
* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-22
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Improved make rules for profiling and debuggingClifford Wolf2013-11-22
* Updated abcClifford Wolf2013-11-21
* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-21
* Fixed async proc detection in mem2regClifford Wolf2013-11-21
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Fixed a bug in "add -global_input"Clifford Wolf2013-11-21
* Added "proc_arst -global_arst" featureClifford Wolf2013-11-20
* Fixed ilang parser: memory widthClifford Wolf2013-11-20
* Added "add" command (only wires for now)Clifford Wolf2013-11-20
* Another name resolution bugfix for generate blocksClifford Wolf2013-11-20
* Implemented indexed part selectsClifford Wolf2013-11-20
* Do not allow memory bit select on the left side of an assignmentClifford Wolf2013-11-20
* Added "synthesis" in (synopsys|synthesis) comment supportClifford Wolf2013-11-20
* Fixed name resolution of local tasks and functions in generate blockClifford Wolf2013-11-20
* Implemented part/bit select on memory readClifford Wolf2013-11-20
* Updated TODOs in README fileClifford Wolf2013-11-20
* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-20
* Added "make config-sudo"Clifford Wolf2013-11-19
* Install simlib in datdirClifford Wolf2013-11-19
* Large improvements in yosys-configClifford Wolf2013-11-19
* Fixed parsing of module arguments when one type is used for many argsClifford Wolf2013-11-19
* Renamed temp module generated by "abc" pass from "logic" to "netlist"Clifford Wolf2013-11-19
* Added additional mem2reg testcaseClifford Wolf2013-11-18
* Fixed two bugs in mem2reg functionality in AST frontendClifford Wolf2013-11-18
* Added dumping of attributes in AST frontendClifford Wolf2013-11-18
* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
* Fixed mem2reg for reg usage outside always blockClifford Wolf2013-11-18
* Added commented-out osu025 maping commands to cmos techmap exampleClifford Wolf2013-11-18
* Added -v<level> option and some minor driver cleanupsClifford Wolf2013-11-17
* Renamed ABCHGPULL to ABCPULL in MakefileClifford Wolf2013-11-16
* Improved building of yosys-abcClifford Wolf2013-11-13
* Fixed abc pass blif parser for constant bitsClifford Wolf2013-11-13
* Fixed parsing of "parameter integer"Clifford Wolf2013-11-13
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* Added information on all internal cell types to internal checkerClifford Wolf2013-11-11
* Call internal checker more oftenClifford Wolf2013-11-10
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09
* Silenced a gcc warning in spice backendClifford Wolf2013-11-09
* Added verification of SAT model to "eval -vloghammer_report" commandClifford Wolf2013-11-09
* More undef-propagation related fixesClifford Wolf2013-11-08
* Fixed handling of different signedness in power operandsClifford Wolf2013-11-08
* Fixed keep attribute on wires in opt_cleanClifford Wolf2013-11-08
* Implemented const folding of ternary op with undef selectClifford Wolf2013-11-08
* Removed debug log from const_pow()Clifford Wolf2013-11-08
* Fixed handling of power operatorClifford Wolf2013-11-07