yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22
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*	Added more performance measurement infrastructure	Clifford Wolf	2013-11-22
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*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵	Clifford Wolf	2013-11-22
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*	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	Clifford Wolf	2013-11-22
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*	Added SigBit struct and refactored RTLIL::SigSpec::extract	Clifford Wolf	2013-11-22
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*	Improved make rules for profiling and debugging	Clifford Wolf	2013-11-22
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*	Updated abc	Clifford Wolf	2013-11-21
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*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21
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*	Fixed async proc detection in mem2reg	Clifford Wolf	2013-11-21
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
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*	Fixed a bug in "add -global_input"	Clifford Wolf	2013-11-21
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*	Added "proc_arst -global_arst" feature	Clifford Wolf	2013-11-20
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*	Fixed ilang parser: memory width	Clifford Wolf	2013-11-20
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*	Added "add" command (only wires for now)	Clifford Wolf	2013-11-20
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*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20
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*	Implemented indexed part selects	Clifford Wolf	2013-11-20
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*	Do not allow memory bit select on the left side of an assignment	Clifford Wolf	2013-11-20
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*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20
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*	Fixed name resolution of local tasks and functions in generate block	Clifford Wolf	2013-11-20
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
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*	Updated TODOs in README file	Clifford Wolf	2013-11-20
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*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20
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*	Added "make config-sudo"	Clifford Wolf	2013-11-19
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*	Install simlib in datdir	Clifford Wolf	2013-11-19
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*	Large improvements in yosys-config	Clifford Wolf	2013-11-19
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*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19
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*	Renamed temp module generated by "abc" pass from "logic" to "netlist"	Clifford Wolf	2013-11-19
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*	Added additional mem2reg testcase	Clifford Wolf	2013-11-18
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*	Fixed two bugs in mem2reg functionality in AST frontend	Clifford Wolf	2013-11-18
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*	Added dumping of attributes in AST frontend	Clifford Wolf	2013-11-18
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*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18
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*	Fixed mem2reg for reg usage outside always block	Clifford Wolf	2013-11-18
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*	Added commented-out osu025 maping commands to cmos techmap example	Clifford Wolf	2013-11-18
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*	Added -v<level> option and some minor driver cleanups	Clifford Wolf	2013-11-17
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*	Renamed ABCHGPULL to ABCPULL in Makefile	Clifford Wolf	2013-11-16
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*	Improved building of yosys-abc	Clifford Wolf	2013-11-13
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*	Fixed abc pass blif parser for constant bits	Clifford Wolf	2013-11-13
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*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13
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*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
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*	Added information on all internal cell types to internal checker	Clifford Wolf	2013-11-11
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*	Call internal checker more often	Clifford Wolf	2013-11-10
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*	Improved user-friendliness of "sat" and "eval" expression parsing	Clifford Wolf	2013-11-09
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*	Silenced a gcc warning in spice backend	Clifford Wolf	2013-11-09
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*	Added verification of SAT model to "eval -vloghammer_report" command	Clifford Wolf	2013-11-09
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*	More undef-propagation related fixes	Clifford Wolf	2013-11-08
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*	Fixed handling of different signedness in power operands	Clifford Wolf	2013-11-08
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*	Fixed keep attribute on wires in opt_clean	Clifford Wolf	2013-11-08
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*	Implemented const folding of ternary op with undef select	Clifford Wolf	2013-11-08
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*	Removed debug log from const_pow()	Clifford Wolf	2013-11-08
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*	Fixed handling of power operator	Clifford Wolf	2013-11-07
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