Commit message (Expand)AuthorAge
* Various equiv_simple improvementsClifford Wolf2015-01-22
* Moved equiv stuff to passes/equiv/Clifford Wolf2015-01-22
* Progress in equiv_simpleClifford Wolf2015-01-21
* Fixed opt_muxtree performance bugClifford Wolf2015-01-21
* Faster "make clean-abc"Clifford Wolf2015-01-20
* README stuffClifford Wolf2015-01-20
* Added equiv_simpleClifford Wolf2015-01-19
* Added equiv_statusClifford Wolf2015-01-19
* Added equiv_make commandClifford Wolf2015-01-19
* Added $equiv cell typeClifford Wolf2015-01-19
* Merge branch 'master' of Wolf2015-01-18
| * Merge pull request #47 from mschmoelzer/masterClifford Wolf2015-01-18
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| | * Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.Martin Schmölzer2015-01-18
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* | Various cleanups in xilinx techlibClifford Wolf2015-01-18
* | Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-18
* improvements in muxtree/select_leaves testClifford Wolf2015-01-18
* Improvements in opt_muxtreeClifford Wolf2015-01-18
* More opt_muxtree cleanupsClifford Wolf2015-01-18
* Added hashlib::idict<>Clifford Wolf2015-01-18
* Various cleanups and improvements in opt_muxtreeClifford Wolf2015-01-18
* Added synth_xilinx -retime -flattenClifford Wolf2015-01-17
* Added support for memories to flatten (techmap)Clifford Wolf2015-01-17
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-17
* Fixed a bug in opt_muxtree for "mux forests"Clifford Wolf2015-01-17
* Improved opt_muxtreeClifford Wolf2015-01-17
* Optimizing no-op cell->setPort()Clifford Wolf2015-01-17
* Bugfix in dff2dffeClifford Wolf2015-01-16
* Added cells.libClifford Wolf2015-01-16
* Added dff2dffe to synth_xilinxClifford Wolf2015-01-16
* Added more FF types to xilinx/cells.vClifford Wolf2015-01-16
* Fixed xilinx bram clock inverted configClifford Wolf2015-01-16
* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-16
* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-15
* Added "abc -lut w1:w2"Clifford Wolf2015-01-15
* Fixed handling of foo.__TECHMAP_...Clifford Wolf2015-01-15
* Ignoring more system task and functionsClifford Wolf2015-01-15
* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-15
* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-15
* Various cleanups in synth_xilinx commandClifford Wolf2015-01-13
* Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)Clifford Wolf2015-01-13
* Tiny fix in vcdcd.plClifford Wolf2015-01-13
* Small Makefile typo fixClifford Wolf2015-01-13
* Only enable code coverage counters on linuxClifford Wolf2015-01-09
* Merge pull request #46 from utzig/masterClifford Wolf2015-01-08
| * Enable use of homebrew's provided bison if availableFabio Utzig2015-01-08
| * Enable bison to be customizedFabio Utzig2015-01-08
| * Add homebrew's libffi pathsFabio Utzig2015-01-08
| * Add homebrew's readline pathsFabio Utzig2015-01-08
* Added add_share_file Makefile macroClifford Wolf2015-01-08
* added minimalistic xilinx sim modelsClifford Wolf2015-01-08