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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Various fixes and improvements in "write_smt2 -bv"Clifford Wolf2014-12-25
* Added "test_cell -muxdiv"Clifford Wolf2014-12-25
* Various fixes and improvements in write_smt2Clifford Wolf2014-12-25
* Added "test_cell -w" featureClifford Wolf2014-12-25
* Fixed simplemap for $ne cells with output width > 1Clifford Wolf2014-12-25
* Added support for most BV cell types to write_smt2Clifford Wolf2014-12-25
* Added "write_smt2 -bv" and other write_smt2 improvementsClifford Wolf2014-12-25
* Fixed off-by-one bug in "hierarchy -check" for positional module argsClifford Wolf2014-12-24
* Added write_smt2 (only gate level logic supported so far)Clifford Wolf2014-12-24
* Added "dfflibmap -prepare" helpClifford Wolf2014-12-24
* Added "dfflibmap -prepare"Clifford Wolf2014-12-24
* Added "dff2dffe -direct" for direct gate mappingClifford Wolf2014-12-24
* Added "dff2dffe -unmap"Clifford Wolf2014-12-24
* Added support for gate-level cells in dff2dffeClifford Wolf2014-12-24
* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-24
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
* Improved ABC clock domain partitioningClifford Wolf2014-12-23
* Indenting fix in show.ccClifford Wolf2014-12-23
* Added "show -colorattr"Clifford Wolf2014-12-23
* Added "abc -markgroups"Clifford Wolf2014-12-23
* Added support for multiple clock domains to "abc" passClifford Wolf2014-12-21
* Fixed "abc" pass for clk and enable signals driven by logicClifford Wolf2014-12-21
* Added DFFE support to "abc" passClifford Wolf2014-12-20
* Added $dffe support to write_verilogClifford Wolf2014-12-20
* Checking existence of ports in "hierarchy -check"Clifford Wolf2014-12-19
* Fixed another bug in write_blif handling of $lut cellsClifford Wolf2014-12-19
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-12-17
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| * Fixed build with gcc 4.6Clifford Wolf2014-12-16
* | Fixed writing of $lut cells in BLIF backendClifford Wolf2014-12-17
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* Added "write_blif -undef" and support for special "-" true/false/undef typeClifford Wolf2014-12-14
* Added "write_blif -blackbox"Clifford Wolf2014-12-14
* Added "blif -unbuf" featureClifford Wolf2014-12-14
* Removed psmisc from deps list (usually fuser is already installed and the pac...Clifford Wolf2014-12-14
* Added psmisc to prerequisitesClifford Wolf2014-12-12
* Removed UTF-8 chars from techmap.vClifford Wolf2014-12-12
* Added missing prerequisites to READMEClifford Wolf2014-12-12
* Added IdString::destruct_guard hackClifford Wolf2014-12-11
* Compile fix for visual studioClifford Wolf2014-12-11
* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-11
* Added functionality to dff2dffe passClifford Wolf2014-12-08
* Added bool constructors to SigBit and SigSpecClifford Wolf2014-12-08
* Added module->addDffe() and module->addDffeGate()Clifford Wolf2014-12-08
* Added skeleton dff2dffe passClifford Wolf2014-12-08
* Added more documentation fixmes for nontrivial register cellsClifford Wolf2014-12-08
* Added $dffe cell typeClifford Wolf2014-12-08
* Added $_DFFE_??_ cell typesClifford Wolf2014-12-08
* Merge branch 'master' of https://github.com/Martoni/yosysClifford Wolf2014-12-07
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| * manual/presentation.tex: bg option is unknown with beamer 3.3 in beamercolorboxFabien Marteau2014-12-07
* | Merge pull request #43 from Martoni/masterClifford Wolf2014-12-06
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