Commit message (Expand)AuthorAge
* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-15
* Added "abc -lut w1:w2"Clifford Wolf2015-01-15
* Fixed handling of foo.__TECHMAP_...Clifford Wolf2015-01-15
* Ignoring more system task and functionsClifford Wolf2015-01-15
* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-15
* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-15
* Various cleanups in synth_xilinx commandClifford Wolf2015-01-13
* Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)Clifford Wolf2015-01-13
* Tiny fix in vcdcd.plClifford Wolf2015-01-13
* Small Makefile typo fixClifford Wolf2015-01-13
* Only enable code coverage counters on linuxClifford Wolf2015-01-09
* Merge pull request #46 from utzig/masterClifford Wolf2015-01-08
| * Enable use of homebrew's provided bison if availableFabio Utzig2015-01-08
| * Enable bison to be customizedFabio Utzig2015-01-08
| * Add homebrew's libffi pathsFabio Utzig2015-01-08
| * Add homebrew's readline pathsFabio Utzig2015-01-08
* Added add_share_file Makefile macroClifford Wolf2015-01-08
* added minimalistic xilinx sim modelsClifford Wolf2015-01-08
* disabled problematic mux -> and/or transformClifford Wolf2015-01-07
* More Xilinx bram cleanupsClifford Wolf2015-01-07
* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-07
* memory_bram hotfix for memories with width 1Clifford Wolf2015-01-06
* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06
* small fix in xilinx/brams.vClifford Wolf2015-01-06
* fixed compiler warning on non-linux archsClifford Wolf2015-01-06
* removed old debug codeClifford Wolf2015-01-06
* hashlib iterator fixClifford Wolf2015-01-06
* build fix for mxeClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06
* Various small improvements to synth_xilinxClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06
* dict<> ref vs insert bugfixClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-05
* Towards Xilinx bram supportClifford Wolf2015-01-04
* Added memory_bram "shuffle_enable" featureClifford Wolf2015-01-04
* Removed left over debug code from memory_bramClifford Wolf2015-01-04
* Fixed pattern matching in "hierarchy -generate"Clifford Wolf2015-01-04
* Print non-errors to stdoutClifford Wolf2015-01-03
* Added "memory -bram"Clifford Wolf2015-01-03
* Added memory_bram 'or_next_if_better' featureClifford Wolf2015-01-03
* memory_bram transp supportClifford Wolf2015-01-03
* Progress in memory_bramClifford Wolf2015-01-03
* Cosmetic changes in verilog output formatClifford Wolf2015-01-02
* Added proper clkpol support to memory_bramClifford Wolf2015-01-02
* Fixes and improvements in bram testClifford Wolf2015-01-02
* Progress in bram testbenchClifford Wolf2015-01-02
* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-02
* New $mem simlib modelClifford Wolf2015-01-02