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| * Renamed yosys-show temp files to be dot-files in the users home directoryClifford Wolf2013-06-12
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| * Fixed gcc build (c++11 stuff in ezSAT)Clifford Wolf2013-06-12
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* | Another fix for a bug found using xsthammerClifford Wolf2013-06-12
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* Further improved and extended xsthammerClifford Wolf2013-06-11
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* More xsthammer improvementsClifford Wolf2013-06-10
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* More sign-extension related fixesClifford Wolf2013-06-10
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* Sign-extension related fixes in SatGen and AST frontendClifford Wolf2013-06-10
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* Progress xsthammer scriptsClifford Wolf2013-06-10
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* Improvements and fixes in SAT codeClifford Wolf2013-06-10
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* Added history file read/write to driverClifford Wolf2013-06-10
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* Progress in xsthammer: working proof for cell modelsClifford Wolf2013-06-10
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* Fixes and improvements in AST const foldingClifford Wolf2013-06-10
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* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
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* Fixed generation of newlines in "dump" outputClifford Wolf2013-06-10
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* Added "rename" commandClifford Wolf2013-06-10
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* Progress on xsthammerClifford Wolf2013-06-10
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* Added first xsthammer scriptsClifford Wolf2013-06-10
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* Renamed "sat_solve" pass to "sat"Clifford Wolf2013-06-09
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* Implemented temporal induction proofs in sat_solveClifford Wolf2013-06-09
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* Added support for non-temporal proofs to sat_solveClifford Wolf2013-06-09
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* Re-organization in sat_solver pass for temporal inductionClifford Wolf2013-06-09
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* Added ezSAT api support for don't care values in modelsClifford Wolf2013-06-09
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* Fixed handling of $_XOR_ in SAT generatorClifford Wolf2013-06-09
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* Added sequential solving support to sat_solveClifford Wolf2013-06-09
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* Set rl_basic_word_break_characters in shellClifford Wolf2013-06-09
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* Improved readline tab completionClifford Wolf2013-06-09
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* Look for yosys-abc and yosys-svgviewer where the main exe isClifford Wolf2013-06-09
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* Added "make abc" and "make install-abc"Clifford Wolf2013-06-08
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* Moved cmds from kernel/ to passes/cmds/Clifford Wolf2013-06-08
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* Fixed typo is sat_solve help msgClifford Wolf2013-06-08
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* Added support for shifter cells to SAT generatorClifford Wolf2013-06-08
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* Added "cd" and "ls" commands for convenienceClifford Wolf2013-06-08
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* Various improvements in sat_solve pass and SAT generatorClifford Wolf2013-06-08
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* Added -all and -max options to sat_solveClifford Wolf2013-06-08
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* Fixes and improvements in ezSAT libraryClifford Wolf2013-06-08
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* Improved auto-detection of -show signals in sat_solveClifford Wolf2013-06-08
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* Improved sat generator and sat_solve passClifford Wolf2013-06-07
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* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
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* Added ezSAT libraryClifford Wolf2013-06-07
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* Renamed opt_rmunused to opt_cleanClifford Wolf2013-06-05
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* Implemented technology mapping for multipliers (using array multiplier)Clifford Wolf2013-06-03
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* Added "dump" command (part ilang backend)Clifford Wolf2013-06-02
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* Fixed techmap/flatten for positional module argumentsClifford Wolf2013-05-26
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* Improved log messages generated by hierarchy passClifford Wolf2013-05-26
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* Added -nodetect option to fsm passClifford Wolf2013-05-24
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* Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.vClifford Wolf2013-05-24
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* Improved FSM one-hot encoding, added binary encodingClifford Wolf2013-05-24
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* Added log_assert() apiClifford Wolf2013-05-24
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* Added log_abort() apiClifford Wolf2013-05-24
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* Fixed a gcc vs. clang determinism problem in abc passClifford Wolf2013-05-23
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