yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23
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*	Fixed "make clean" for manual files	Clifford Wolf	2013-07-23
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*	Added web site link to README	Clifford Wolf	2013-07-21
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*	Added Yosys Manual	Clifford Wolf	2013-07-20
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*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12
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*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12
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*	Added ast frontend refactoring to TODO	Clifford Wolf	2013-07-11
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*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11
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*	Bugfixes for empty signal vectors	Clifford Wolf	2013-07-10
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*	Fixed sign propagation in bit-wise operators	Clifford Wolf	2013-07-09
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*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09
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\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
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* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07
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*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07
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*	Removed tests/xsthammer	Clifford Wolf	2013-07-07
\| \| \| \| \|	This test is now available as 'vloghammer' in a seperate repository: https://github.com/cliffordwolf/VlogHammer
*	Added opt_clean -purge option	Clifford Wolf	2013-07-07
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*	Fixed handling of $eq and $ne in opt_const	Clifford Wolf	2013-07-07
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*	Fixed vivado related xsthammer bugs	Clifford Wolf	2013-07-05
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*	Various improvements in xsthammer report generator	Clifford Wolf	2013-07-05
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*	Added work-around to isim bug in xsthammer report script	Clifford Wolf	2013-07-05
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*	Fixed gcc warnings in ezminisat	Clifford Wolf	2013-07-05
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*	Added CARRY4 Xilinx cell to xsthammer cell lib	Clifford Wolf	2013-07-05
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*	Added xsthammer report generator	Clifford Wolf	2013-07-05
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*	Improved xsthammer quartus support	Clifford Wolf	2013-07-04
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*	Added Altera Cyclon III cell library to xsthammer	Clifford Wolf	2013-07-04
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*	Documentation updates	Clifford Wolf	2013-07-04
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
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*	Added QMAKE makefile variable	Clifford Wolf	2013-07-03
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*	Added Altera Quartus support to xsthammer	Clifford Wolf	2013-07-03
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*	Progress in xsthammer	Clifford Wolf	2013-07-03
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*	Added vivado support to xsthammer	Clifford Wolf	2013-06-26
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*	Added SAT support for -all/-max with -verify	Clifford Wolf	2013-06-23
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-06-20
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\| *	Added renaming of wires and cells to "rename" command	Clifford Wolf	2013-06-19
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* \|	Added timout functionality to SAT solver	Clifford Wolf	2013-06-20
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*	Added "eval" pass	Clifford Wolf	2013-06-19
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*	Fixed build with clang	Clifford Wolf	2013-06-18
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*	Added splitnets command	Clifford Wolf	2013-06-18
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*	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	Clifford Wolf	2013-06-18
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*	Added more stuff to xsthammer, found first xst bug	Clifford Wolf	2013-06-17
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*	Added support for "assign" statements in abc vlparse	Clifford Wolf	2013-06-15
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*	Added ternary op and concat op to xsthammer	Clifford Wolf	2013-06-15
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*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14
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*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13
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*	More xsthammer improvements (using xst 14.5 now)	Clifford Wolf	2013-06-13
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-06-12
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\| *	Added "scatter" command	Clifford Wolf	2013-06-12
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