yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Fixed xilinx/example_sim_counter test bench	Clifford Wolf	2013-11-24
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*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24
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*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24
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*	Removed now obsolete test cases	Clifford Wolf	2013-11-24
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
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*	Added modelsim support to autotest	Clifford Wolf	2013-11-24
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*	Fixed "flatten" top-module detection: Only use on fully selected designs	Clifford Wolf	2013-11-24
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*	Fixed "make install" dependencies	Clifford Wolf	2013-11-24
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
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*	Updated command-reference-manual.tex	Clifford Wolf	2013-11-23
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*	AppNote 010 typo fixes and corrections	Clifford Wolf	2013-11-23
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*	AppNote 010 progress	Clifford Wolf	2013-11-23
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*	Improved handling of techmap special wires	Clifford Wolf	2013-11-23
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*	Improved handling of initialized registers	Clifford Wolf	2013-11-23
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*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23
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*	Making prograss on Appnote 010	Clifford Wolf	2013-11-23
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*	Progress on AppNote 010	Clifford Wolf	2013-11-22
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*	Started to write on AppNote 010: Verilog to BLIF	Clifford Wolf	2013-11-22
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*	Updated command-reference-manual.tex	Clifford Wolf	2013-11-22
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Some driver changes/fixes	Clifford Wolf	2013-11-22
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*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22
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*	Added more performance measurement infrastructure	Clifford Wolf	2013-11-22
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*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵	Clifford Wolf	2013-11-22
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*	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	Clifford Wolf	2013-11-22
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*	Added SigBit struct and refactored RTLIL::SigSpec::extract	Clifford Wolf	2013-11-22
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*	Improved make rules for profiling and debugging	Clifford Wolf	2013-11-22
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*	Updated abc	Clifford Wolf	2013-11-21
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*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21
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*	Fixed async proc detection in mem2reg	Clifford Wolf	2013-11-21
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
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*	Fixed a bug in "add -global_input"	Clifford Wolf	2013-11-21
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*	Added "proc_arst -global_arst" feature	Clifford Wolf	2013-11-20
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*	Fixed ilang parser: memory width	Clifford Wolf	2013-11-20
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*	Added "add" command (only wires for now)	Clifford Wolf	2013-11-20
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*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20
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*	Implemented indexed part selects	Clifford Wolf	2013-11-20
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*	Do not allow memory bit select on the left side of an assignment	Clifford Wolf	2013-11-20
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*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20
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*	Fixed name resolution of local tasks and functions in generate block	Clifford Wolf	2013-11-20
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
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*	Updated TODOs in README file	Clifford Wolf	2013-11-20
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*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20
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*	Added "make config-sudo"	Clifford Wolf	2013-11-19
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*	Install simlib in datdir	Clifford Wolf	2013-11-19
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*	Large improvements in yosys-config	Clifford Wolf	2013-11-19
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*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19
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*	Renamed temp module generated by "abc" pass from "logic" to "netlist"	Clifford Wolf	2013-11-19
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*	Added additional mem2reg testcase	Clifford Wolf	2013-11-18
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