yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04
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*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03
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*	Added "wreduce" to some of the standard test benches	Clifford Wolf	2014-08-03
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*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03
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*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03
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*	Added query() API to ModIndex	Clifford Wolf	2014-08-03
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*	Added ID() macro for static IdStrings	Clifford Wolf	2014-08-03
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*	Implemented recursive techmap	Clifford Wolf	2014-08-03
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*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03
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*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02
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*	Fixed a va_list corruption in logv_error()	Clifford Wolf	2014-08-02
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*	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02
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*	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02
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*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
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*	Limit size of log_signal buffer to 100 elements	Clifford Wolf	2014-08-02
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*	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02
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*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02
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*	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02
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*	Fixed memory corruption related to id2cstr()	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
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*	Added logfile hash to statistics footer	Clifford Wolf	2014-08-01
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
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*	Added per-pass cpu usage statistics	Clifford Wolf	2014-08-01
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01
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*	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01
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*	Consolidated hana test benches into fewer files	Clifford Wolf	2014-08-01
\| \| \| \| \| \| \| \|	for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module ", sprintf("module f%d_",ARGIND)); print; }' \ ${pf}__test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done; ..etc..
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01
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*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31
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*	Various cleanups in Makefile, Renamed default configurations	Clifford Wolf	2014-07-31
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*	Added compiler + compiler version + compiler flags to version string	Clifford Wolf	2014-07-31
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*	Fixed build of verific bindings	Clifford Wolf	2014-07-31
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added "trace" command	Clifford Wolf	2014-07-31
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*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
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*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31
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*	Added "techmap -assert"	Clifford Wolf	2014-07-31
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*	Reorganized stdcells.v (no actual code change, just moved and indented stuff)	Clifford Wolf	2014-07-31
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*	Added "yosys -A"	Clifford Wolf	2014-07-31
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*	Added "yosys -Q"	Clifford Wolf	2014-07-31
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30
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*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30
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*	Added write_file command	Clifford Wolf	2014-07-30
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*	Added "make -j{N}" support to "make test"	Clifford Wolf	2014-07-30
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