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* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-20
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| * Added hilomap commandClifford Wolf2014-01-19
| * Added sat -tempinduc and sat -prove-assertsClifford Wolf2014-01-19
| * Added $assert support to satgenClifford Wolf2014-01-19
| * Added $assert cellClifford Wolf2014-01-19
| * Added Verilog parser support for assertsClifford Wolf2014-01-19
| * Fixed $lut simlib model for a wider range of toolsClifford Wolf2014-01-18
| * Fixed parsing of verilog macros at end of lineClifford Wolf2014-01-18
| * More changes to simlib to make it friendlier to a wider range of toolsClifford Wolf2014-01-18
| * Fixed a type in $mem model in simlib.vClifford Wolf2014-01-18
* | script addedAhmed Irfan2014-01-18
* | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-18
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| * \ Merge branch 'master' of https://github.com/ahmedirfan1983/yosysAhmed Irfan2014-01-18
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| * \ \ Merge branch 'master' of https://github.com/cliffordwolf/yosysAhmed Irfan2014-01-18
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* | | | pmux2muxAhmed Irfan2014-01-18
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| * | | Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-18
| * | | Added $bu0 cell to simlib.vClifford Wolf2014-01-18
| * | | Improved setundef random number generatorClifford Wolf2014-01-18
| * | | Added setundef commandClifford Wolf2014-01-17
| * | | Some improvements in log_dump_val_worker() templatesClifford Wolf2014-01-17
| * | | Added techlibs/common/pmux2mux.vClifford Wolf2014-01-17
* | | | verilog default options pullAhmed Irfan2014-01-17
* | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-17
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| * | | Merge pull request #4 from cliffordwolf/masterAhmed Irfan2014-01-17
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| | * | Added verilog_defaults commandClifford Wolf2014-01-17
| | * | Added support for $adff with undef data inputs to opt_rmdffClifford Wolf2014-01-17
| | * | Added select -assert-none and -assert-anyClifford Wolf2014-01-17
* | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-17
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| * | | Merge pull request #3 from cliffordwolf/masterAhmed Irfan2014-01-17
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| | * Added automatic memid generation to memory_unpack commandClifford Wolf2014-01-17
| | * Added memory_unpack commandClifford Wolf2014-01-17
* | | slice error correctedAhmed Irfan2014-01-16
* | | width issuesAhmed Irfan2014-01-15
* | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-15
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| * | Merge pull request #2 from cliffordwolf/masterAhmed Irfan2014-01-15
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| | * Merge pull request #20 from mschmoelzer/masterClifford Wolf2014-01-14
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| | | * Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))Martin Schmölzer2014-01-14
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| | * Added hierarchy -libdir optionClifford Wolf2014-01-14
| | * renamed LibertyParer to LibertyParserClifford Wolf2014-01-14
| | * Added "+" to list of liberty token charactersClifford Wolf2014-01-14
* | | BTOR backendAhmed Irfan2014-01-14
* | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-14
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| * | Merge pull request #1 from cliffordwolf/masterAhmed Irfan2014-01-14
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| | * Added "opt_const -mux_undef"Clifford Wolf2014-01-14
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| * Fixed typo in frontends/ast/simplify.ccClifford Wolf2014-01-12
| * Improved performance of freduce input cone reductionClifford Wolf2014-01-04
| * Improved freduce performance on const signalsClifford Wolf2014-01-04
| * Performance improvements in freduce passClifford Wolf2014-01-03
| * More freduce cleanupsClifford Wolf2014-01-03
| * Added updating of RTLIL::autoidx to ilang frontendClifford Wolf2014-01-03