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Debian dgit repo for package yosys
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Ahmed Irfan
2014-01-20
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Added hilomap command
Clifford Wolf
2014-01-19
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Added sat -tempinduc and sat -prove-asserts
Clifford Wolf
2014-01-19
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Added $assert support to satgen
Clifford Wolf
2014-01-19
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Added $assert cell
Clifford Wolf
2014-01-19
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Added Verilog parser support for asserts
Clifford Wolf
2014-01-19
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Fixed $lut simlib model for a wider range of tools
Clifford Wolf
2014-01-18
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Fixed parsing of verilog macros at end of line
Clifford Wolf
2014-01-18
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More changes to simlib to make it friendlier to a wider range of tools
Clifford Wolf
2014-01-18
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Fixed a type in $mem model in simlib.v
Clifford Wolf
2014-01-18
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script added
Ahmed Irfan
2014-01-18
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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
Ahmed Irfan
2014-01-18
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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys
Ahmed Irfan
2014-01-18
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Merge branch 'master' of https://github.com/cliffordwolf/yosys
Ahmed Irfan
2014-01-18
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pmux2mux
Ahmed Irfan
2014-01-18
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Removed cases of trailing comma in stdcells.v
Clifford Wolf
2014-01-18
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Added $bu0 cell to simlib.v
Clifford Wolf
2014-01-18
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Improved setundef random number generator
Clifford Wolf
2014-01-18
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Added setundef command
Clifford Wolf
2014-01-17
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Some improvements in log_dump_val_worker() templates
Clifford Wolf
2014-01-17
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Added techlibs/common/pmux2mux.v
Clifford Wolf
2014-01-17
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verilog default options pull
Ahmed Irfan
2014-01-17
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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
Ahmed Irfan
2014-01-17
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Merge pull request #4 from cliffordwolf/master
Ahmed Irfan
2014-01-17
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Added verilog_defaults command
Clifford Wolf
2014-01-17
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Added support for $adff with undef data inputs to opt_rmdff
Clifford Wolf
2014-01-17
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Added select -assert-none and -assert-any
Clifford Wolf
2014-01-17
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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
Ahmed Irfan
2014-01-17
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Merge pull request #3 from cliffordwolf/master
Ahmed Irfan
2014-01-17
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Added automatic memid generation to memory_unpack command
Clifford Wolf
2014-01-17
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Added memory_unpack command
Clifford Wolf
2014-01-17
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slice error corrected
Ahmed Irfan
2014-01-16
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width issues
Ahmed Irfan
2014-01-15
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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
Ahmed Irfan
2014-01-15
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Merge pull request #2 from cliffordwolf/master
Ahmed Irfan
2014-01-15
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Merge pull request #20 from mschmoelzer/master
Clifford Wolf
2014-01-14
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Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))
Martin Schmölzer
2014-01-14
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Added hierarchy -libdir option
Clifford Wolf
2014-01-14
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renamed LibertyParer to LibertyParser
Clifford Wolf
2014-01-14
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Added "+" to list of liberty token characters
Clifford Wolf
2014-01-14
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BTOR backend
Ahmed Irfan
2014-01-14
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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
Ahmed Irfan
2014-01-14
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Merge pull request #1 from cliffordwolf/master
Ahmed Irfan
2014-01-14
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Added "opt_const -mux_undef"
Clifford Wolf
2014-01-14
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Fixed typo in frontends/ast/simplify.cc
Clifford Wolf
2014-01-12
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Improved performance of freduce input cone reduction
Clifford Wolf
2014-01-04
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Improved freduce performance on const signals
Clifford Wolf
2014-01-04
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Performance improvements in freduce pass
Clifford Wolf
2014-01-03
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More freduce cleanups
Clifford Wolf
2014-01-03
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Added updating of RTLIL::autoidx to ilang frontend
Clifford Wolf
2014-01-03
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