yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Using $pos models for $bu0	Clifford Wolf	2014-09-03
*	Fixed "test_cells -vlog"	Clifford Wolf	2014-09-03
*	Fixes in $alu SAT- and eval-models	Clifford Wolf	2014-09-03
*	Undef-related fixes in simlib $alu model	Clifford Wolf	2014-09-02
*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02
*	Added test_cell -vlog	Clifford Wolf	2014-09-02
*	Create a default selection stack in RTLIL::Design::Design()	Clifford Wolf	2014-09-02
*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02
*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02
*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02
*	Removed yosys-svgviewer	Clifford Wolf	2014-09-02
*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02
*	Added $alu support to test_cell	Clifford Wolf	2014-09-01
*	Added ConstEval model for $alu cells	Clifford Wolf	2014-09-01
*	Added SAT model for $alu cells	Clifford Wolf	2014-09-01
*	Fixed "test_cell -simlib all"	Clifford Wolf	2014-09-01
*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01
*	Added "techmap -autoproc"	Clifford Wolf	2014-09-01
*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01
*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01
*	Added eval testing to test_cell	Clifford Wolf	2014-08-31
*	Fixed return size of const_*() eval functions	Clifford Wolf	2014-08-31
*	Added RTLIL::Const::size()	Clifford Wolf	2014-08-31
*	Added eval model for $lut cells	Clifford Wolf	2014-08-31
*	Typo fixes in cell->*Param() API	Clifford Wolf	2014-08-31
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31
*	Added design->scratchpad	Clifford Wolf	2014-08-30
*	Added $alu cell type	Clifford Wolf	2014-08-30
*	Added autotest -e (do not use -noexpr on write_verilog)	Clifford Wolf	2014-08-30
*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30
*	Fixed module->addPmux()	Clifford Wolf	2014-08-30
*	Using worker class in memory_map	Clifford Wolf	2014-08-30
*	Replaced $__alu CO/CS outputs with full-width CO output	Clifford Wolf	2014-08-30
*	Don't change existing binary FSM encoding if it is already optimal	Clifford Wolf	2014-08-30
*	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	Clifford Wolf	2014-08-30
*	Improved handling of $pmux cells in fsm_extract	Clifford Wolf	2014-08-30
*	Fixed inserting of Q-inverters in dfflibmap	Clifford Wolf	2014-08-27
*	Fixed printing of multi-line Makefile.conf	Clifford Wolf	2014-08-27
*	Implemented "rename -enumerate -pattern"	Clifford Wolf	2014-08-26
*	Print Makefile.conf as make info message	Clifford Wolf	2014-08-26
*	Checking for valid CONFIG value in Makefile	Clifford Wolf	2014-08-25
*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24
*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24
*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24
*	azonenberg: Make dump_vcd save model when temporal induction fails due to ste...	Clifford Wolf	2014-08-24
*	Only call proc_share_dirname() in techmap when necessary	Clifford Wolf	2014-08-23
*	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	Clifford Wolf	2014-08-23
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23