Commit message (Expand)AuthorAge
* Improved comments on topological sort in edif backendClifford Wolf2013-11-04
* Fixes for early width and sign detection in ast simplifierClifford Wolf2013-11-04
* further improved early width and sign detection in ast simplifierClifford Wolf2013-11-04
* Added simple topological sort to edif backendClifford Wolf2013-11-03
* Write yosys version to output filesClifford Wolf2013-11-03
* Merge branch 'master' of Wolf2013-11-03
| * Added resolution of positional arguments to hierarchy passClifford Wolf2013-11-03
| * Ignore explicit unconnected ports in intersynth backendClifford Wolf2013-11-03
* | Fixed detectSignWidthWorker (ast frontend) for AST_CONCATClifford Wolf2013-11-03
* | Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...Clifford Wolf2013-11-02
* | Added roadmap to readme fileClifford Wolf2013-11-02
* | Various ast changes for early expression width detection (prep for constfold ...Clifford Wolf2013-11-02
* | Added DFFSR cell to techlibs/cmos/cmos_cells.libClifford Wolf2013-10-31
* | Added placeholder check to dfflibmap and cleaned up some other placeholder ch...Clifford Wolf2013-10-31
* | Changed MiniSAT feater defines againClifford Wolf2013-10-31
* Added paragraph to README file to avoid mycells.lib confusionClifford Wolf2013-10-31
* README file typo fixClifford Wolf2013-10-31
* Some additions to the README fileClifford Wolf2013-10-31
* Fixed ezminisat C++ errors: undef PRIi64Clifford Wolf2013-10-30
* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-30
* Fixed help message typo (memory pass)Clifford Wolf2013-10-30
* Added -format option to splitnetsClifford Wolf2013-10-29
* Merge pull request #12 from jameswalmsley/masterClifford Wolf2013-10-27
| * [EXAMPLES] Ported the mojo counter example to Zynq ZED board.James Walmsley2013-10-27
* Fixed get_share_file_name() for installed yosysClifford Wolf2013-10-27
* Cleanups in xilinx examplesClifford Wolf2013-10-27
* Added synth_xilinx commandClifford Wolf2013-10-27
* Added API and Makefile rules for share/ filesClifford Wolf2013-10-27
* Added design->full_selection() helper methodClifford Wolf2013-10-27
* Moved simple xilinx counter sim example to subdirClifford Wolf2013-10-27
* Xilinx mojo_counter example is now workingClifford Wolf2013-10-27
* Fixed hex string generation bug in edif backendClifford Wolf2013-10-27
* Renamed techlibs/xilinx7 to techlibs/xilinxClifford Wolf2013-10-26
* Improved xilinx mojo_counter exampleClifford Wolf2013-10-26
* Added support for i/o buffers to iopadmapClifford Wolf2013-10-26
* Added another xilinx example (not funcional yet)Clifford Wolf2013-10-26
* Added support for sr flip-flops to dfflibmapClifford Wolf2013-10-24
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
* Fixed parsing of value-less attributes in ilangClifford Wolf2013-10-23
* Improved handling of dff with async resetsClifford Wolf2013-10-21
* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-19
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-18
* Added dffsr support to proc_dff passClifford Wolf2013-10-18
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-18
* Bugfix in dffsr techmap rulesClifford Wolf2013-10-18
* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-18