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* Improved comments on topological sort in edif backendClifford Wolf2013-11-04
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* Fixes for early width and sign detection in ast simplifierClifford Wolf2013-11-04
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* further improved early width and sign detection in ast simplifierClifford Wolf2013-11-04
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* Added simple topological sort to edif backendClifford Wolf2013-11-03
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* Write yosys version to output filesClifford Wolf2013-11-03
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-11-03
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| * Added resolution of positional arguments to hierarchy passClifford Wolf2013-11-03
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| * Ignore explicit unconnected ports in intersynth backendClifford Wolf2013-11-03
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* | Fixed detectSignWidthWorker (ast frontend) for AST_CONCATClifford Wolf2013-11-03
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* | Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing ↵Clifford Wolf2013-11-02
| | | | | | | | before constfold fixes)
* | Added roadmap to readme fileClifford Wolf2013-11-02
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* | Various ast changes for early expression width detection (prep for constfold ↵Clifford Wolf2013-11-02
| | | | | | | | fixes)
* | Added DFFSR cell to techlibs/cmos/cmos_cells.libClifford Wolf2013-10-31
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* | Added placeholder check to dfflibmap and cleaned up some other placeholder ↵Clifford Wolf2013-10-31
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* | Changed MiniSAT feater defines againClifford Wolf2013-10-31
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* Added paragraph to README file to avoid mycells.lib confusionClifford Wolf2013-10-31
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* README file typo fixClifford Wolf2013-10-31
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* Some additions to the README fileClifford Wolf2013-10-31
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* Fixed ezminisat C++ errors: undef PRIi64Clifford Wolf2013-10-30
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* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-30
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* Fixed help message typo (memory pass)Clifford Wolf2013-10-30
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* Added -format option to splitnetsClifford Wolf2013-10-29
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* Merge pull request #12 from jameswalmsley/masterClifford Wolf2013-10-27
|\ | | | | [EXAMPLES] Ported the mojo counter example to Zynq ZED board.
| * [EXAMPLES] Ported the mojo counter example to Zynq ZED board.James Walmsley2013-10-27
|/ | | | Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
* Fixed get_share_file_name() for installed yosysClifford Wolf2013-10-27
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* Cleanups in xilinx examplesClifford Wolf2013-10-27
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* Added synth_xilinx commandClifford Wolf2013-10-27
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* Added API and Makefile rules for share/ filesClifford Wolf2013-10-27
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* Added design->full_selection() helper methodClifford Wolf2013-10-27
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* Moved simple xilinx counter sim example to subdirClifford Wolf2013-10-27
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* Xilinx mojo_counter example is now workingClifford Wolf2013-10-27
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* Fixed hex string generation bug in edif backendClifford Wolf2013-10-27
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* Renamed techlibs/xilinx7 to techlibs/xilinxClifford Wolf2013-10-26
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* Improved xilinx mojo_counter exampleClifford Wolf2013-10-26
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* Added support for i/o buffers to iopadmapClifford Wolf2013-10-26
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* Added another xilinx example (not funcional yet)Clifford Wolf2013-10-26
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* Added support for sr flip-flops to dfflibmapClifford Wolf2013-10-24
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* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
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* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
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* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-24
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* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
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* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
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* Fixed parsing of value-less attributes in ilangClifford Wolf2013-10-23
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* Improved handling of dff with async resetsClifford Wolf2013-10-21
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* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-19
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* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-18
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* Added dffsr support to proc_dff passClifford Wolf2013-10-18
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* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-18
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* Bugfix in dffsr techmap rulesClifford Wolf2013-10-18
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* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-18
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